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how to achieve single-end clock input with CDCM7005 ?

Conan Cheng
Prodigy 10 points
Other Parts Discussed in Thread: CDCM7005

I want to use a VXCO which is single-end clock output, and I find that CDCM7005 provides VBB Bias voltage output for Singel-ended input signals.I want to know how to use "VBB" pin when Singel-ended input signal is us

  • 0
    TI__Expert 4150 points

    VBB can indeed provide the biasing for the unused, 2nd input. I think you should do the following:

    VCXO output  --> AC coupling cap --> VCXO_INP

    VCXO_INP --> 10kΩ --> VCXO_INN

    VBB --> VCXO_INN

    VBB --> decoupling cap --> GND

     

    So basically the VBB signal biases the N-input, and you AC couple the VCXO to the P-input. The 10k allows to also bias the P-input the the exact same voltage as the N-input, so that the input duty cycle will be exactly 50%.

    Best regards, Fritz

  • 0 in reply to Fritz
    Intellectual 400 points
    The input pins for the VXCO pins are LVPECL aren't they? The common mode bias for this logic is ~ 1.2volts, the datasheet states that the bias from VBB is VCC - 1.3 volts, in my case that will put it at 2V.

    Will the approach above work for this case as well? Or do I need to reduce the bias on VBB to 1.2Volts? Please advise.

    Dave Durachka
    NASA GSFC
  • 0 in reply to Fritz
    Prodigy 70 points
    can you share that arrangement picture, it will be very useful
  • 0 in reply to Naveen kumar
    Intellectual 400 points

    Here you go.  The values of Cac and Cct will vary depending upon your frequency of operation.  Rdc will typically be 50-ohms for most VCO's, but that may also vary.