CDCE6214: frequency steps

Stefan,

1. What is the fastest way to mute and unmute an output? In the datasheet it says you can appoint a GPIO to the OUTPUT enable function, but it takes 4 clock cycles for the output to be actually muted, and 4 clock cycles for the output to be switched on again after the output enable is asserted again. Is this correct? the SYNCN pin can also be used to mute the outputs. Is the behavior different?
   1. If only changing the output dividers, then enable the glitchless mode on the pin and change the divider as required:
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   2.  If changing the VCO frequency by modifying the PLL settings, then disable the outputs, modify the PLL settings as desired, recalibrate the PLL, then re-enable the outputs:
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   3. If only synchronizing the outputs, the SYNC bit can be used for synchronization of the outputs in cycles of the prescaler period, as is shown below. The behavior here is different:
      
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2. It is possible to continuously increase/decrease the frequency of the output clock with a frequency step defined in a register. GPIOs can be set as input for increasing/decreasing the frequency with predetermined steps, and a rising edge will toggle the increase/decrease with one step. What is the fastest frequency with which these rising edges can be sent to the CDCE6214 GPIOs?
   1. The pulse width must meet the minimum criteria of 10 ns (i.e. at least 10 ns high pulse, then 10 ns low pulse):
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Thanks,

Kadeem