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CDCI6214: It cannot generate expected clocks

Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214


I wish to generate 2MHz clocks from channel 2 and 3. But the measured output clocks are always 760KHz. The input is 80MHz LVDS ac-coupled input.

Below figure is block diagram in TISC Pro. The input is bypassed to Y0. I can measure an 80MHz clock. So I don’t know why the outputs are 760KHz. The PLL is unlocked, but I tried several options, on one can lock it.


80MHz output at Y0

760KHz output