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CDCE6214-Q1: cdce6214-q1

yang fengxiao
Prodigy 20 points

Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCE6214

When writing my own burn program, which registers should I confirm write successfully by read back value equal to write value?

I tested to burn EEPROM from a file:

Fullscreen cdce6214_SG100_DPCLK_HexRegisterValues.txt Download 
R85	0x00550000
R84	0x00540000
R83	0x0053FB00
R82	0x005205C0
R81	0x00510004
R80	0x00500000
R79	0x004F0008
R78	0x004E1000
R77	0x004D0000
R76	0x004C0008
R75	0x004B0008
R74	0x004AA181
R73	0x00493000
R72	0x00480006
R71	0x00470000
R70	0x00460008
R69	0x0045A181
R68	0x00443000
R67	0x00430006
R66	0x00420000
R65	0x00410008
R64	0x0040A181
R63	0x003F3000
R62	0x003E0006
R61	0x003D0000
R60	0x003C0008
R59	0x003B0008
R58	0x003A502C
R57	0x00395000
R56	0x00380006
R55	0x0037001E
R54	0x00363400
R53	0x00350069
R52	0x00345000
R51	0x003340C0
R50	0x003207C0
R49	0x00310013
R48	0x003023C7
R47	0x002F0380
R46	0x002E0000
R45	0x002D4F80
R44	0x002C0318
R43	0x002B0051
R42	0x002A0002
R41	0x00290000
R40	0x00280000
R39	0x00270000
R38	0x00260000
R37	0x00250000
R36	0x00240000
R35	0x00230028
R34	0x00220000
R33	0x00210000
R32	0x00200000
R31	0x001F0000
R30	0x001E0060
R29	0x001D0000
R28	0x001C0000
R27	0x001B0004
R26	0x001A0000
R25	0x00190401
R24	0x00180024
R23	0x00170406
R22	0x001600A2
R21	0x00150583
R20	0x00140000
R19	0x00130000
R18	0x00120000
R17	0x001126C4
R16	0x0010921F
R15	0x000FA037
R14	0x000EB364
R13	0x000D003F
R12	0x000C7002
R11	0x000B0000
R10	0x000A0000
R9	0x0009B364
R8	0x00080001
R7	0x0007042C
R6	0x00060DAC
R5	0x00050008
R4	0x00040000
R3	0x00030000
R2	0x00020002
R1	0x00012310
R0	0x00001000

The result shows:

Fullscreen result.txt Download 
row:0/86 cmd:0x0055 retdata=0x0000, expected=0x0000, OK(Masked)
row:1/86 cmd:0x0054 retdata=0x0000, expected=0x0000, OK(Masked)
row:2/86 cmd:0x0053 retdata=0xff00, expected=0xfb00, Mismatch(Masked)
row:3/86 cmd:0x0052 retdata=0x01c0, expected=0x05c0, Mismatch(Masked)
row:4/86 cmd:0x0051 retdata=0x0004, expected=0x0004, OK(Masked)
row:5/86 cmd:0x0050 retdata=0x0000, expected=0x0000, OK(Masked)
row:6/86 cmd:0x004f retdata=0x0008, expected=0x0008, OK(Masked)
row:7/86 cmd:0x004e retdata=0x1000, expected=0x1000, OK(Masked)
row:8/86 cmd:0x004d retdata=0x0000, expected=0x0000, OK(Masked)
row:9/86 cmd:0x004c retdata=0x0008, expected=0x0008, OK(Masked)
row:10/86 cmd:0x004b retdata=0x0008, expected=0x0008, OK(Masked)
row:11/86 cmd:0x004a retdata=0xa181, expected=0xa181, OK(Masked)
row:12/86 cmd:0x0049 retdata=0x3000, expected=0x3000, OK(Masked)
row:13/86 cmd:0x0048 retdata=0x0006, expected=0x0006, OK(Masked)
row:14/86 cmd:0x0047 retdata=0x0000, expected=0x0000, OK(Masked)
row:15/86 cmd:0x0046 retdata=0x0008, expected=0x0008, OK(Masked)
row:16/86 cmd:0x0045 retdata=0xa181, expected=0xa181, OK(Masked)
row:17/86 cmd:0x0044 retdata=0x3000, expected=0x3000, OK(Masked)
row:18/86 cmd:0x0043 retdata=0x0006, expected=0x0006, OK(Masked)
row:19/86 cmd:0x0042 retdata=0x0000, expected=0x0000, OK(Masked)
row:20/86 cmd:0x0041 retdata=0x0008, expected=0x0008, OK(Masked)
row:21/86 cmd:0x0040 retdata=0xa181, expected=0xa181, OK(Masked)
row:22/86 cmd:0x003f retdata=0x3000, expected=0x3000, OK(Masked)
row:23/86 cmd:0x003e retdata=0x0006, expected=0x0006, OK(Masked)
row:24/86 cmd:0x003d retdata=0x0000, expected=0x0000, OK(Masked)
row:25/86 cmd:0x003c retdata=0x0008, expected=0x0008, OK(Masked)
row:26/86 cmd:0x003b retdata=0x0008, expected=0x0008, OK(Masked)
row:27/86 cmd:0x003a retdata=0x502c, expected=0x502c, OK(Masked)
row:28/86 cmd:0x0039 retdata=0x5000, expected=0x5000, OK(Masked)
row:29/86 cmd:0x0038 retdata=0x0006, expected=0x0006, OK(Masked)
row:30/86 cmd:0x0037 retdata=0x001e, expected=0x001e, OK(Masked)
row:31/86 cmd:0x0036 retdata=0x3400, expected=0x3400, OK(Masked)
row:32/86 cmd:0x0035 retdata=0x0069, expected=0x0069, OK(Masked)
row:33/86 cmd:0x0034 retdata=0x5000, expected=0x5000, OK(Masked)
row:34/86 cmd:0x0033 retdata=0x40c0, expected=0x40c0, OK(Masked)
row:35/86 cmd:0x0032 retdata=0x07c0, expected=0x07c0, OK(Masked)
row:36/86 cmd:0x0031 retdata=0x0013, expected=0x0013, OK(Masked)
row:37/86 cmd:0x0030 retdata=0x23c7, expected=0x23c7, OK(Masked)
row:38/86 cmd:0x002f retdata=0x0380, expected=0x0380, OK(Masked)
row:39/86 cmd:0x002e retdata=0x0000, expected=0x0000, OK(Masked)
row:40/86 cmd:0x002d retdata=0x4f80, expected=0x4f80, OK(Masked)
row:41/86 cmd:0x002c retdata=0x0318, expected=0x0318, OK(Masked)
row:42/86 cmd:0x002b retdata=0x0051, expected=0x0051, OK(Masked)
row:43/86 cmd:0x002a retdata=0x0002, expected=0x0002, OK(Masked)
row:44/86 cmd:0x0029 retdata=0x0000, expected=0x0000, OK(Masked)
row:45/86 cmd:0x0028 retdata=0x0000, expected=0x0000, OK(Masked)
row:46/86 cmd:0x0027 retdata=0x0000, expected=0x0000, OK(Masked)
row:47/86 cmd:0x0026 retdata=0x0000, expected=0x0000, OK(Masked)
row:48/86 cmd:0x0025 retdata=0x0000, expected=0x0000, OK(Masked)
row:49/86 cmd:0x0024 retdata=0x0000, expected=0x0000, OK(Masked)
row:50/86 cmd:0x0023 retdata=0x0058, expected=0x0028, Mismatch(Masked)
row:51/86 cmd:0x0022 retdata=0x0000, expected=0x0000, OK(Masked)
row:52/86 cmd:0x0021 retdata=0x0000, expected=0x0000, OK(Masked)
row:53/86 cmd:0x0020 retdata=0x0000, expected=0x0000, OK(Masked)
row:54/86 cmd:0x001f retdata=0x0000, expected=0x0000, OK(Masked)
row:55/86 cmd:0x001e retdata=0x0060, expected=0x0060, OK(Masked)
row:56/86 cmd:0x001d retdata=0x0000, expected=0x0000, OK(Masked)
row:57/86 cmd:0x001c retdata=0x0000, expected=0x0000, OK(Masked)
row:58/86 cmd:0x001b retdata=0x0004, expected=0x0004, OK(Masked)
row:59/86 cmd:0x001a retdata=0x0000, expected=0x0000, OK(Masked)
row:60/86 cmd:0x0019 retdata=0x0401, expected=0x0401, OK(Masked)
row:61/86 cmd:0x0018 retdata=0x0024, expected=0x0024, OK(Masked)
row:62/86 cmd:0x0017 retdata=0x0406, expected=0x0406, OK(Masked)
row:63/86 cmd:0x0016 retdata=0x00a2, expected=0x00a2, OK(Masked)
row:64/86 cmd:0x0015 retdata=0x0593, expected=0x0583, Mismatch(Masked)
row:65/86 cmd:0x0014 retdata=0x0000, expected=0x0000, OK(Masked)
row:66/86 cmd:0x0013 retdata=0x0000, expected=0x0000, OK(Masked)
row:67/86 cmd:0x0012 retdata=0x0000, expected=0x0000, OK(Masked)
row:68/86 cmd:0x0011 retdata=0x26c4, expected=0x26c4, OK(Masked)
row:69/86 cmd:0x0010 retdata=0x921f, expected=0x921f, OK(Masked)
row:70/86 cmd:0x000f retdata=0xa037, expected=0xa037, OK(Masked)
row:71/86 cmd:0x000e retdata=0xa95b, expected=0xb364, Mismatch(Masked)
row:72/86 cmd:0x000d retdata=0x003f, expected=0x003f, OK(Masked)
row:73/86 cmd:0x000c retdata=0x7002, expected=0x7002, OK(Masked)
row:74/86 cmd:0x000b retdata=0x0000, expected=0x0000, OK(Masked)
row:75/86 cmd:0x000a retdata=0xa95b, expected=0x0000, Mismatch(Masked)
row:76/86 cmd:0x0009 retdata=0xa95b, expected=0xb364, Mismatch(Masked)
row:77/86 cmd:0x0008 retdata=0x0001, expected=0x0001, OK(Masked)
row:78/86 cmd:0x0007 retdata=0x0d0d, expected=0x042c, Mismatch(Masked)
row:79/86 cmd:0x0006 retdata=0x0eec, expected=0x0dac, Mismatch(Masked)
row:80/86 cmd:0x0005 retdata=0x0008, expected=0x0008, OK(Masked)
row:81/86 cmd:0x0004 retdata=0x0000, expected=0x0000, OK(Masked)
row:82/86 cmd:0x0003 retdata=0x1000, expected=0x0000, Mismatch(Masked)
row:83/86 cmd:0x0002 retdata=0x0002, expected=0x0002, OK(Masked)
row:84/86 cmd:0x0001 retdata=0x2310, expected=0x2310, OK(Masked)
row:85/86 cmd:0x0000 retdata=0x0000, expected=0x1000, Mismatch(Masked)

It looks like many registers read back is not equal to what I wrote! Among those registers that mismatch, many registers has no definition in both datasheet or TICS Pro tool.

Can TI provide a list contain which registers we should not confirm or should not write, expecially those registers have no definition?

  • 0
    TI__Mastermind 23280 points

    Yang,

    In the datasheet, this list is available in Table 21:

    The values listed in this table should be the same before and after EEPROM programming. Any other fields would be the default value in the registers document.

    Is EEPROM programming successful with the TICS Pro tool? Can you try with writing all registers and using the register commit flow instead of the direct access flow?


    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 20 points

    Hi Kadeem:

    Thanks! 

    Table 21 represenets part of the R85-R0 RW bits stored in EEPROM! I summarized Table 21 bits and will use it to compare data.

    Let me try to update my program and check if any mismatch occurs.

    BTW, I suggest the datasheet should be more clear that Table21 is not all register layout in EEPROM, but is the RW bits should be compared in EEPROM.

  • 0 in reply to Kadeem Samuel
    Prodigy 20 points

    Hi Kadeem：

    I updated my program with new algorithm:

    1. add EEPROM RW bits definition mask array, add PAGE1 defaul value int array
    2. when register defined in mask array, use mask to compare expected data and returned data
    3. when register not defined in mask array, use default value to compare returned data

    Finally, all of the masked values are compared correctly, but some of default value compare failed!

    Fullscreen cdce6214_newburnlog.txt Download 
    Step Final/10: verify all regs(except uncheckable regs)...
row:00/86 cmd:0x0055 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:01/86 cmd:0x0054 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:02/86 cmd:0x0053 retdata=0xff00, expected=0xfb00, default=0xff00 OK(Default)
row:03/86 cmd:0x0052 retdata=0x01c0, expected=0x05c0, default=0x01c0 OK(Default)
row:04/86 cmd:0x0051 retdata=0x0004, expected=0x0004, default=0x0004 OK(Masked)
row:05/86 cmd:0x0050 retdata=0x0000, expected=0x0000, default=0x0008 OK(Masked)
row:06/86 cmd:0x004f retdata=0x0008, expected=0x0008, default=0x0008 OK(Masked)
row:07/86 cmd:0x004e retdata=0x1000, expected=0x1000, default=0x0000 OK(Masked)
row:08/86 cmd:0x004d retdata=0x0000, expected=0x0000, default=0x0002 OK(Masked)
row:09/86 cmd:0x004c retdata=0x0008, expected=0x0008, default=0x0188 OK(Masked)
row:10/86 cmd:0x004b retdata=0x0008, expected=0x0008, default=0x8008 OK(Masked)
row:11/86 cmd:0x004a retdata=0xa181, expected=0xa181, default=0xa181 OK(Masked)
row:12/86 cmd:0x0049 retdata=0x3000, expected=0x3000, default=0x0000 OK(Masked)
row:13/86 cmd:0x0048 retdata=0x0006, expected=0x0006, default=0x0006 OK(Masked)
row:14/86 cmd:0x0047 retdata=0x0000, expected=0x0000, default=0x0406 OK(Masked)
row:15/86 cmd:0x0046 retdata=0x0008, expected=0x0008, default=0x0808 OK(Masked)
row:16/86 cmd:0x0045 retdata=0xa181, expected=0xa181, default=0xa181 OK(Masked)
row:17/86 cmd:0x0044 retdata=0x3000, expected=0x3000, default=0x0000 OK(Masked)
row:18/86 cmd:0x0043 retdata=0x0006, expected=0x0006, default=0x0006 OK(Masked)
row:19/86 cmd:0x0042 retdata=0x0000, expected=0x0000, default=0x0006 OK(Masked)
row:20/86 cmd:0x0041 retdata=0x0008, expected=0x0008, default=0x4808 OK(Masked)
row:21/86 cmd:0x0040 retdata=0xa181, expected=0xa181, default=0xa181 OK(Masked)
row:22/86 cmd:0x003f retdata=0x3000, expected=0x3000, default=0x0000 OK(Masked)
row:23/86 cmd:0x003e retdata=0x0006, expected=0x0006, default=0x0006 OK(Masked)
row:24/86 cmd:0x003d retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:25/86 cmd:0x003c retdata=0x0008, expected=0x0008, default=0x6028 OK(Masked)
row:26/86 cmd:0x003b retdata=0x0008, expected=0x0008, default=0x8008 OK(Masked)
row:27/86 cmd:0x003a retdata=0x502c, expected=0x502c, default=0x502c OK(Masked)
row:28/86 cmd:0x0039 retdata=0x5000, expected=0x5000, default=0x0000 OK(Masked)
row:29/86 cmd:0x0038 retdata=0x0006, expected=0x0006, default=0x0006 OK(Masked)
row:30/86 cmd:0x0037 retdata=0x001e, expected=0x001e, default=0x001e OK(Masked)
row:31/86 cmd:0x0036 retdata=0x3400, expected=0x3400, default=0x3400 OK(Default)
row:32/86 cmd:0x0035 retdata=0x0069, expected=0x0069, default=0x0069 OK(Masked)
row:33/86 cmd:0x0034 retdata=0x5000, expected=0x5000, default=0x5000 OK(Default)
row:34/86 cmd:0x0033 retdata=0x40c0, expected=0x40c0, default=0x40c0 OK(Masked)
row:35/86 cmd:0x0032 retdata=0x07c0, expected=0x07c0, default=0x01c0 OK(Masked)
row:36/86 cmd:0x0031 retdata=0x0013, expected=0x0013, default=0x0013 OK(Masked)
row:37/86 cmd:0x0030 retdata=0x23c7, expected=0x23c7, default=0x1a05 OK(Masked)
row:38/86 cmd:0x002f retdata=0x0380, expected=0x0380, default=0x0280 OK(Masked)
row:39/86 cmd:0x002e retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:40/86 cmd:0x002d retdata=0x4f80, expected=0x4f80, default=0x4f80 OK(Default)
row:41/86 cmd:0x002c retdata=0x0318, expected=0x0318, default=0x0318 OK(Default)
row:42/86 cmd:0x002b retdata=0x0051, expected=0x0051, default=0x0051 OK(Masked)
row:43/86 cmd:0x002a retdata=0x0002, expected=0x0002, default=0x0002 OK(Masked)
row:44/86 cmd:0x0029 retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:45/86 cmd:0x0028 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:46/86 cmd:0x0027 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:47/86 cmd:0x0026 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:48/86 cmd:0x0025 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:49/86 cmd:0x0024 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:50/86 cmd:0x0023 retdata=0x0058, expected=0x0028, default=0x0058 OK(Default)
row:51/86 cmd:0x0022 retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:52/86 cmd:0x0021 retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:53/86 cmd:0x0020 retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:54/86 cmd:0x001f retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:55/86 cmd:0x001e retdata=0x0060, expected=0x0060, default=0x0030 OK(Masked)
row:56/86 cmd:0x001d retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:57/86 cmd:0x001c retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:58/86 cmd:0x001b retdata=0x0004, expected=0x0004, default=0x0004 OK(Masked)
row:59/86 cmd:0x001a retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:60/86 cmd:0x0019 retdata=0x0401, expected=0x0401, default=0x0400 OK(Masked)
row:61/86 cmd:0x0018 retdata=0x0024, expected=0x0024, default=0x091c OK(Masked)
row:62/86 cmd:0x0017 retdata=0x0406, expected=0x0406, default=0x2406 Mismatch(Default)
row:63/86 cmd:0x0016 retdata=0x00a2, expected=0x00a2, default=0x06a2 Mismatch(Default)
row:64/86 cmd:0x0015 retdata=0x0583, expected=0x0583, default=0x0513 Mismatch(Default)
row:65/86 cmd:0x0014 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:66/86 cmd:0x0013 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:67/86 cmd:0x0012 retdata=0x0000, expected=0x0000, default=0x0000 OK(Default)
row:68/86 cmd:0x0011 retdata=0x26c4, expected=0x26c4, default=0x26c4 OK(Default)
row:69/86 cmd:0x0010 retdata=0x921f, expected=0x921f, default=0x921f OK(Default)
row:70/86 cmd:0x000f retdata=0xa037, expected=0xa037, default=0xa037 OK(Masked)
row:71/86 cmd:0x000e retdata=0xc9c2, expected=0xb364, default=0x0000 OK(Masked)
row:72/86 cmd:0x000d retdata=0x003f, expected=0x003f, default=0x0000 OK(Masked)
row:73/86 cmd:0x000c retdata=0x7002, expected=0x7002, default=0x7002 OK(Default)
row:74/86 cmd:0x000b retdata=0x0000, expected=0x0000, default=0x003f Mismatch(Default)
row:75/86 cmd:0x000a retdata=0xc9c2, expected=0x0000, default=0xa777 OK(Masked)
row:76/86 cmd:0x0009 retdata=0xc9c2, expected=0xb364, default=0xa777 OK(Masked)
row:77/86 cmd:0x0008 retdata=0x0001, expected=0x0001, default=0x0001 OK(Default)
row:78/86 cmd:0x0007 retdata=0x0d0d, expected=0x042c, default=0x0c0d Mismatch(Default)
row:79/86 cmd:0x0006 retdata=0x0eec, expected=0x0dac, default=0x0e6c Mismatch(Default)
row:80/86 cmd:0x0005 retdata=0x0008, expected=0x0008, default=0x0008 OK(Masked)
row:81/86 cmd:0x0004 retdata=0x0000, expected=0x0000, default=0x0000 OK(Masked)
row:82/86 cmd:0x0003 retdata=0x1000, expected=0x0000, default=0x0200 OK(Masked)
row:83/86 cmd:0x0002 retdata=0x0002, expected=0x0002, default=0x0000 OK(Masked)
row:84/86 cmd:0x0001 retdata=0x2310, expected=0x2310, default=0x7652 OK(Masked)
row:85/86 cmd:0x0000 retdata=0x1000, expected=0x1000, default=0x2000 OK(Masked)

    As to these registers: R35,R23,R22,R21,R6. Datasheet has not definition in Table-21, so I used Page1 default value to check, but it looks like the default value in datasheet is not equal to what I read back. Why?

    I'm not sure if I should compare those not defined in Table-21.Can I only check those defined in Table-21 by mask, and skip all of other registers? It will directly solve my problem, but I'm not sure if any value should be verified out of the Table-21.

  • 0 in reply to yang fengxiao
    TI__Mastermind 23280 points

    Yang,

    I have checked the values of the internal-only fields in the registers R35 ,R23, R22, R21, & R6 (in addition to any of the "mismatch" fields). There is no issue with these being different - many of these are for internal status bits.

    R7 will differ depending on the current lock status.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 20 points

    Hi Kadeem:

    Thanks！But I‘m concerned that for another burn file on a different CDCE6214, checking default value for many registers may not be trustable. For example, I found R6 mismatch, I can manually skip R6 or update check value to 0xeec, but what if it becomes another value at a different device? What if another '(Default)' register ,like R17 mismatch occurs? I need to develope a robust verify flow. 

    Can I skip check all of the registers that are not defined in Table-21? In other word, only check those registers in my test log with "(Masked)" at the end of line. I think this solution will solve my problem, but I'm not sure is it enough to cover all of the configuration of the burn file?

    Those "undefined registers" like a black box for us users, but they are not equal what we write and varies from default value after burn, which causes us can not use default value to check them. The only solution I can think of is to skip all of the 'black box registers'. Can you give some suggestion?

  • +1 in reply to yang fengxiao
    TI__Expert 6415 points

    Hello Yang, 

    Yes, focusing on only what is listed in Table 21 should ensure proper verification of the EEPROM configuration. The registers outside of that table can vary in value and do not properly reflect the state of the burn file configuration [for example, R6]. Additionally, it's important to take into consideration the bits highlighted in red in Table 21 that are device specific and may vary from part to part.

    Thanks,

    Cris