LMK04828: About clock output

I think it should be possible by using DCLKout0_POL or SDCLKout1_POL bits to invert the phase of the clock on one of the outputs - I haven't tested this, it may only apply to the SYSREF path or it may introduce some additional propagation delay that shifts the phase apart from 180° exactly. I encourage you to try it out and see what happens. Otherwise, the only programmatic way would be to set the SYSREF divider to the same divide value as the clock divider, and use digital delay to synchronize the phase to the desired offset - depending on your configuration this might not be possible, and there'd be a phase noise penalty on the SYSREF clock due to the different divider architecture used.

If you have the option to specify layout, you could swap the P/N pins on one of the outputs. This would be true 180° phase inversion.