CDCE6214Q1TM: Different output frequency from Multiple output simultaneously.

Hi,

I am working on a Xilinx FPGA based board which has major interfaces like SFP (Optical communication) and PCIe Gen4. Below are my clocking requirements for the interfaces.

1. 156.25MHz - For SFP protocol
2. 100MHz - For PCIe Gen4
3. 125Mhz - For PCIe Gen4

Input Frequency- 100Mhz from PCIe connector

I have planned to use CDCE6214Q1TM for generating the above clocks. Below is the image for your reference. Also there are few other solutions offered by the tool, I have attached the pdf for your easy reference.

As per design specification, I can use this IC (or similar IC) only if it can be controlled using control pins and not using any serial programming interface.

So request you to kindly confirm if the input and output configuration be decided only using control pins and not using any serial programming.

Do I have control on the individual outputs and their output frequency.

Can I generate different output frequencies from different outputs simultaneously? just using programmable pins instead of serial communication?

I have attached the simulation results which can achieved by using different IC's.

Please validate and let me know if this is the right way to take it further ahead.

Jitter Spec- 

100M & 125MHz PCIE clock- 0.5ps RMS

Regards

Krishna Kumar C

3_OP_100_156_125_12results.pdfCDCE6214-Q1_100_156_125.pdf