CDCE913 output clock behavior when updating frequency setting

Filip Roth

Other Parts Discussed in Thread: CDCE913

We are considering using the CDCE913 for video clock generation. For our project we need to be able to adjust the frequency of the clock source smoothly, for example when changing from 80MHz to 81MHz we need the clock to smoothly transition to the new settings, with no output clock signal interruptions and with only small changes in duty cycle and period. In ideal case the clock period _n_ would be with old setting and clock period _n+1_ with the new setting. Is this possible with the CDCE913 if we would only change the frequency in small steps (few percent max) ?

Thank you for Your answer

Best regards

Filip Roth

over 14 years ago

0 Julian Hagedorn over 14 years ago

TI__Mastermind 20900 points

Hello Filip,

sorry for the late reply, we will look into this.

1) What are the finest frequency steps you want to have?

2) Or do you just want to have a smooth transition without missing some clock periods? If this it the case, then you can simply switch between two PLL-register settings. This will allow the PLL to smoothly lock at the new frequency.

Best regards,

Julian

0 Filip Roth over 13 years ago in reply to Julian Hagedorn

Prodigy 20 points

Hello Julian,

we need a smooth transition with no glitches. So i suppose we can use the PLL register switch method.

Thanks for help

Best regards

Filip

Clock & timing

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CDCE913 output clock behavior when updating frequency setting