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LMK04832: clock configuration

alen
Prodigy 80 points
Part Number: LMK04832

Hi:

     In my design, I use an external 200M crystal oscillator connected to CLK_in0 as the reference clock input for LMK04832. The OSCout outputs 200M as the working clock for the FPGA, ensuring that the FPGA can operate after power-on and configuring the LMK04832. I will use DCLK out2 as the 100M ADC_clk output, SDCLK out3 as the SYSREF output, and DCLK out8, DCLK out10, DCLK out12, SDCLK out9, SDCLK out11 as the 100M FPGA DDR4 controller input reference clocks. I will use the 0 delay mode to ensure all output clocks have a fixed phase relationship. I have installed TICS Pro and TI PLLatinum Sim, I am learning to use.

  1. If my crystal oscillator performance is good, do I definitely need to use an external VCXO? Do I need to use CVPD-952 as the 200M VCXO? The image shows available frequencies that do not include 200M,does this mean I cannot use it?
  2. I'm not very clear on which pins the feedback circuit of the zero delay mode needs to use( datasheet show that "zero-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX." If choose an internal feedback ,I need not  to make any other external pin connections for the 0 delay mode? if so, I'd like config DCLKout6 as internal feedback ), and how to use PLLatinum Sim determine the capacitance and resistance values of the loop filter. Can you provide a schematic diagram for a dual loop 0 delay mode reference design using an external VCXO? If an external VCXO is not necessary, could you provide a schematic diagram for a single loop 0 delay mode?

  • +1
    TI__Mastermind 33510 points
    1. If your XO performance is good, there's no need for a VCXO. Cases where the cascaded VCXO loop makes sense include when the reference frequency is "dirty" i.e. high noise floor, like with a recovered clock; or cases where the phase detector frequency would normally be too low at the primary PLL, and you want to preserve decent higher-offset noise by substituting everything above PLL1 loop bandwidth with a clean VCXO.

      Since in your case it sounds like PLL1 is unnecessary, I recommend instead driving your XO into OSCin, so that it can easily be buffered onto OSCout. 

    2. Internal feedback requires no other external connections - you just enable the feedback mux, pick the clock output you want to use as feedback, and you're good to go. You don't even have to power up the output buffer for that clock, as long as the divider is running you can use the output as zero delay feedback.

      PLLatinum Sim should represent the 3rd and 4th order loop filter components as "fixed" since these cannot be modified (they are implemented internally). The 1st and 2nd order components (canonically C1, R2, C2) can be modified. I believe PLLatinum Sim has a user's guide, which describes how to use the optimizer to select for desirable settings - I'd constrain the optimizer to yield at least 50° phase margin (for stability guarantees) and target the best jitter performance in your chosen integration bandwidth. You'll find that the highest charge pump settings on PLL2, and the highest valid phase detector frequency you can manage (200MHz) are your best-case. I'll also point out that there's an unmodeled 60pF capacitance built into the output stage of the charge pump, and in many cases this internal C1 capacitance is sufficient for the entire value of C1. PLLatinum Sim doesn't automatically include this, but we set the default C1 capacitance about 60pF higher than EVM defaults.

      I can draw up a schematic if you think you need it, but in terms of external connections, you basically just have 200MHz XO -> OSCin, R2/C2 (and maybe C1) on CPout2 pin, the bypass caps on the LDObyp1/2 pins, and whatever external components are implied by your choice of output format buffer (e.g. LVPECL might use 240Ω emitter biasing resistors).
  • 0 in reply to Derek Payne
    Prodigy 80 points

      Thank you very much for your highly professional response. I will discuss and adjust the circuit design with the PCB engineer on Monday. If there are no further issues, we can close this matter on Monday.

  • 0 in reply to Derek Payne
    Prodigy 80 points

    I didn't mention DCLKout4 and DCLKout6 before, I intend to use them to provide the CW1x and CW16x clocks for the AFE chip. If I select DCLKout6 as the internal feedback, can DCLKout6 still be used for CW16x clock output ?

  • 0 in reply to alen
    TI__Mastermind 33510 points

    You can use CLKout6 for both internal feedback and external clocking simultaneously. I strongly suggest using the highest frequency you can manage for internal feedback if possible, to keep the phase detector frequency at PLL2 high and the phase noise impact from using PLL2 low. If you can make CLKout6 a 200MHz clock, this would be the best case with your XO input frequency.

    Just in case it helps with layout, there's no DCLK/SDCLK distinction on clock outputs for most use cases; both channel divider and SYSREF can be routed to both odd and even channel outputs in any combination. The feedback mux from CLKout6 is actually taking feedback from the channel divider in the CLKout6/7 pair, so you could even use the CLKout6 feedback path if both CLKout6/7 were set to SYSREF outputs.

  • 0 in reply to Derek Payne
    Prodigy 80 points

    I should  set the feedback to DCLKout8， because when DCLKout6 is used as a CW clock, its frequency will change during system operation, while DCLKout8 and DCLKout9 are fixed at 100M for DDR use. Based on the current application,the maximum frequency for the output clock is 100M, and the maximum detector frequency is also limited to 100M, is it feasible？

  • 0 in reply to alen
    TI__Mastermind 33510 points

    It is feasible, but it's not ideal, and you'll see about 3dB in-band increase in phase noise over the region dominated by PLL noise (typically around 10k to 100k carrier offsets).

    Are you sure you need 0-delay mode? 0-delay mode can help to establish a deterministic phase relationship between the input and output clocks, but if your input clock is an XO and you don't have multiple LMK04832s in the system that need to be synchronized, I'm not sure you care about input-to-output phase determinism. If all you need is for all the outputs to achieve a deterministic phase relationship amongst each other, this can be accomplished just by generating a SYNC event, which resets every output divider and the SYSREF divider at the same clock distribution path cycle and gives you programmable delays to align their phases. Then you'd likely be able to take advantage of the higher phase detector frequency through the normal PLL2 N divider path, provided your VCO frequency of choice is a multiple of 200MHz, and you could skip the feedback mux altogether.

  • 0 in reply to Derek Payne
    Prodigy 80 points

    I reviewed the solution again and found that input-to-output phase determinism is indeed not important, it is unnecessary to implement 0-delay mode. Thank you very much for your answer, it's very helpful to me !