Hi
i am using the LVDS Clock lmk61e2-siat
The LVDS clk (circuit1) signals is send to circuit 2 (the circuit 2 has the 100 ohm resistor) via a flex Cable.
before to connect the flex and second circuit, i made an impedance check, to be sure nothing is short.
the resistor read between clk-P and Gnd is 45K ohm
the resistor read between clk-N and gnd is 50 ohm (i expect, it is not correct,and/or maybe the clk is not working correctly)
Do you have a idea what is the impedance From output CLK-P and CLK-N to GNd should be acceptable?
regards