Build low jitter audio clock with air (WiFi) sync

Constantine Musatoff

Other Parts Discussed in Thread: PLL1707, CDCE913, DAC5571

AirPlay or DLNA protocols send clock information from time to time. Because of uncontrolled delays, this clock information has very large jitter. I can cancel it by program algorithm with analyzing large number of such clock info. As end point clock generator I can use PLL1707 with low jitter outputs. But base frequency 27 MHz must be with deviation controled by program with accuracy not greater several ppm and range several hundreds ppm. This base clock must has low jitter and on-fly frequence changes. How I can build this generator?

over 14 years ago

0 Constantine Musatoff over 14 years ago

Intellectual 880 points

I think that DAC5571 and CDCE913 is all I need in. Is it right?

0 mapefer3 over 14 years ago in reply to Constantine Musatoff

TI__Expert 5725 points

It is possible to change the frequency on the fly in very small steps. Theppms of the steps depends on the setup (input frequency, output frequency and output frequency range that needs to be achieved).

Please refer to the application note in the link below for more information:

http://www.ti.com/litv/pdf/scaa105, section 2.

0 Constantine Musatoff over 14 years ago in reply to mapefer3

Intellectual 880 points

Thanks!

I saw this method. But frequency grid in this method is irregular in one or low ppm magnification. A fortiori small frequency step requeries large coefficient changs. Jitter of PLL depends on coefficients. Thus small frequency change will attend jitter change. To avoid PLL lock fault I shall change VCXO smoothly throw filter.

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Build low jitter audio clock with air (WiFi) sync