Is it okay to output DCLKoutX (both positive and negative) and SDCLKoutX (both positive and negative) at a fixed low level during reset?
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Is it okay to output DCLKoutX (both positive and negative) and SDCLKoutX (both positive and negative) at a fixed low level during reset?
Hi Arinori,
Just to clarify, are you talking about the reset pin or power on reset which will load the default register settings for the device? Or is this for the SYNC function to reset the output dividers?
After power on reset, DCLKout 4,6,8, and 10 will be powered on and all other outputs will be powered off according to the default register settings for the LMK04828:
In case you're talking about just resetting the output dividers, during a SYNC pulse the outputs will be in a logic low state (i.e. P outputs will be low, N outputs will be high) based on the selected output format. Let me know if this answers your question.
Regards,
Connor
Thank you for your reply.
This is the operation when reset with the reset pin.
Since the power supply of the device that receives the CLK signal is separate and voltage application when the power is OFF is not allowed, I would like to know whether the output level of both + and - of the CLK signal is 0V in poweroff mode. .
Isn't there a bias voltage applied due to an internal pull-up?
Hi Arinori,
That's correct, both the + and - ends of the CLK output will be 0V if the output format is set to powerdown.
Regards,
Connor