LMX2572LP: LMX2572LP

Shuhei Goto

Expert 4840 points

Part Number: LMX2572LP

Hi team,

Customer have questions.

Could you give answers or comments please?

With regard to datasheet 7.5.2, Do we have to write the R0 register every time I change the N divider, even if FACL_EN in R0 register is set to 1?
How is VCO calibration used? Do we have to select Assist/No Assist to Partial, Close and Full individually?
When I use VCO CORE1, which kind of assistance is better?
Customer found that the larger the N divider, the smaller the spurs. Is the larger the N divider better for noise?
Is there relationship between MASH ORDER and spurs? (Ex: Larger mash order results in smaller spurs)
With regard to datasheet 6.5 (5) "clean OSCin signal", Does PNPLL_ 1/f contain OSCin's phase noise?
With regard to datasheet 6.5 (5), What is N in the PLL_Flat equation?
The higher the OSCin slew rate, the smaller the phase noise.
Is there a relationship between the phase noise of the reference signal and the phase noise of the PLL output?

Kind regards,

Goto

over 1 year ago

0 vicente flores prado over 1 year ago

TI__Mastermind 28912 points

Hi Goto,
1. Yes you will need to recalibrate VCO every time you change N divider value.

2 & 3. VCO calibration depends on application and level of assistance required.

4. That is correct, smaller N divider values will result in lower phase noise (hence smaller spurs)

5. Refer to this post regarding mash order: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/973466/faq-rf-synthesizers-what-is-mash-order-and-how-to-determine-the-suitable-mash-order-in-rf-synthesizers

6. No, that value is strictly for the PLL itself.

7. Given the following note regarding the configuration N must be 60.

8. Yes. If you input a signal that is very poor in regards in phase noise, you will see the output phase noise also suffer.
Jitter cleaners can effectively clean a "dirty reference" using a PLL with very narrow loop BW (usually less than 10Hz) and an extremely clean source such as a VCXO to output a "clean" copy of the dirty reference. If customer is not too familiar with clocking/PLLs good sources are:

1. https://www.deanbanerjeepll.com/files/Deansbook6.pdf

2. TI precision lab videos (Clocks & Timing)

www.ti.com/.../precision-labs.html

Regards,

Vicente

0 Shuhei Goto over 1 year ago in reply to vicente flores prado

TI__Expert 4840 points

Hi Vicente,

Thank you for your kind support!

Customer asked additional two questions,

Could you look at ppt and give comment or answer please?

Many thanks,

Goto

Furuno_LMX2572LP_20240110.pptx

0 vicente flores prado over 1 year ago in reply to Shuhei Goto

TI__Mastermind 28912 points

Hi Goto,
I have a few questions regarding the presentation.

Regarding slide 1:

Regarding slide 2:
The input appears to be 38.4 MHz and customer seems to want an input multiplier of 5 - there are two issues with this.

1.OSCin is too large for a multiplier value of 5.

2. This should not result in a VCO frequency of 96 MHz, unless the R divider value in the input path is 2.

3. What is the input and output frequencies you require?

Regarding slide 3:
VCO calibration doesn't need to reoccur duing FM modulation, only the N value is changing. Sections 7.3.14 & 8.1.8 of DS have more information on FSK modulation. Make sure to follow instructions for I2S in bullet 3:

Regarding slide 5:
I don't think FSK modulation was achieved successfully. The carrier frequency didn't shift it's 156.8 MHz in both images.

Regarding Slide 6 :

Something is definitely off, VCO core 5 has a minimum VCO frequency of 5200 MHz

Regards,

Vicente

0 Shuhei Goto over 1 year ago in reply to vicente flores prado

TI__Expert 4840 points

Hi Vicente,

Thank you for your support.

Regarding to FM modulation,

customer know core4 is appropriate.

However there are a lot spurs when core4.

Could you tell me how to improve this spurs?

Best regards,

Goto

0 vicente flores prado over 1 year ago in reply to Shuhei Goto

TI__Mastermind 28912 points

Hi Goto,
I do anticipate the following Spurs at the following offsets due to your frequency plan:

The issue here is your OSCin frequency.
You can technically get rid of fractional spurs but increasing your denominator to 6000001 for example or by also trying various values for "MASH_SEED."
I have seen that reducing the charge pump will sometimes reduce the size of your spurs if you can deal with them but might not remove them altogether but you're already at the second to lowest charge pump current available.

I do agree, for VCO frequency of 5017.6 MHz corresponds to VCO core4.

Regards,

Vicente