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LMK04832: PLL2 not getting locked.

jay Krishna
Prodigy 10 points

Part Number: LMK04832

Hello, i am using LMK04832 in our design,i am using PLL2 in single loop mode. pll2 getiing locked initially but output clock was not coming.but when i was changed the value of loop filter then clk was coming but pll2  not getting locked because output  clk is slightly varying  and according to the loop filter when i was chenging the value of loop filter then clk is varying but pll2 not getting locked.

i am using this setting-:-

so what is the exact loop filter values for the PLL2 to getting locked on the HW.

  • 0
    TI__Expert 8421 points

    Jay,

    It looks like you are on the right track using PLLatinumSim to generate the Loop Filter components values.  Make sure that the Fosc, input divider, Fpd, and VCO frequency you choose in PLLatinumSim match the values in TicsPro.  In your images, for example, your Fpd is 100 with an R divider value of 1 in PLLatinumSim, but in TicsPro your R divider is 2 and your Fpd is 50.  Also check on your VCO value in TicsPro, it is red and says 100, ensure the proper value of 3200 MHz is written to the registers.  Also ensure that Single-Loop Mode is enabled from the Set Modes tab in TicsPro.  I have attached an image of values generated in PLLatinumSim that should lock the PLL given your configuration and should generate on your side once you click "calculate loop filter".  

    Let me know if you have any further questions,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 10 points

    Hello,now i have settled the R divider and the VCO frequency according to the PLLatium sim software value but when i am enabling the single loop mode from set modes then the PLL2 phase detector frequency is coming 245.76 and PLL2 not getting locked ,refer the screenshot:--

    is the N- divider value should be same according to the R-divider or we have to adjust it manually to lock the PLL?

    and one more thing that when i am calculating the loop filter components value according to the  Fpd ,Kpd,Fvco and clicking on the calculate loop filter value then its giving me these values,refer the screenshot:--

  • 0 in reply to jay Krishna
    TI__Expert 8421 points

    Jay,

    Your capture from PLLatinumSim looks correct.  The reason why your TicsPro is not locking and showing the phase detector frequency at  245.76 is because you selected OSCin for the PLL2 RCLK MUX where you should choose PLL1 CLKinX which has your input 100 MHz signal. 

    Once you correct this your configuration should have PLL2 lock.  I have attached a TicsPro config that that should be setup this way for your convenience.

    Let me know if you have any further questions,

    Will

    Single_Loop_100MHz_input.tcs

  • 0 in reply to William Pfennigwerth
    Prodigy 10 points

    hello,when i am calculating the loop filter components value according to the  Fpd ,Kpd,Fvco and clicking on the calculate loop filter value then its giving me these values,refer the screenshot:--

    is these values are okay?

     

  • 0 in reply to jay Krishna
    TI__Expert 8421 points

    Jay,

    Yes, these values look correct.  Let me know if you have any other questions,

    Will