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CDCE925: Internal load capacitance in Xtal mode

Part Number: CDCE925

I would like to ask a question for the CDCE925.

Now we measured the frequency of the output clock from the CDCE925 as follows.

・Measurement result
In Xtal mode (Vctrl=1.8V)     26.9992MHz
In VCXO mode (Vctrl=0 V)   26.9992MHz
In VCXO mode (Vctrl=0.9V) 27.0011MHz
In VCXO mode (Vctrl=1.8V) 27.0019MHz

・Fixed conditions
CDCE925 external reference crystal                           25.000MHz 10pF
CDCE925 output clock frequency setting                    27.000000MHz
CDCE925 internal load capacitance register setting   8pF
* Other than OFFSET=01h, bit3-2 INCLK settings are not changed.

In the Xtal mode, the internal load capacitance in the CDCE925 seems to be the maximum which is the same as when Vctrl=0V in the VCXO mode.
Is our understanding correct?

If so, we think that we should change the output clock frequency setting for CDCE925 when in the Xtal mode, because of the internal load capacitance.


So, please let me confirm the internal load capacitance in the Xtal mode.

  • Susumu,

    The internal load capacitance is 8pF as specified by your register setting. This value can be changed through 05h[7:3].

    Additionally, I should note that we recommend using the internal load capacitors instead of external ones:

    Here is the app note referenced for more information: www.ti.com/.../scaa085a.pdf

    Best,

    Cris

  • Thank you for your quick reply.

    My question is not how to set the internal capacitance, but why the clock frequency in the Xtal mode is the same as the clock frequency in the VCXO mode with Vctrl=0V.

    Your document "VCXO Application Guideline for CDCE(L)9xx Family" says the internal capacitance can be changed from 0.3xCLon-chip to 1.3xCLon-chip in the VCXO mode.
    According to my measurement, the internal capacitance is set to 1.3xCLon-chip in the Xtal mode.
    Is this correct?

  • Susumu,

    How much load capacitance is your XTAL rated for? When using the CDCE925, the XTAL is seeing parasitic capacitance from the board, capacitance from the external capacitors, and capacitance from the internal capacitance.

    What Cris is referring to is removing the external capacitors and using solely the internal capacitors to load the XTAL. When you do this, are you able to see the full pulling range? This should result in an increased pulling range, as the total capacitance used for loading the XTAL will change more over tuning voltage.

    How pullable is the XTAL that you are using? The pullability is the ratio between the shunt capacity and the motional capacity p = C0/C1. This value should be close to 220 (or less).

    Thanks,

    Kadeem

  • Thank you for your reply.

    In our environment,the situaion of the capacitance is as follows.
      the external capacitance : not used
      the internal capacitance setting : 8pF
      the external Xtal capacitance : 10pF

    And in our measurement, the output clock frequency is changed about 100 ppm by changing the Vctrl from 0 to 1.8V.

    In this situation, is the internal capacitance set to 1.3xCLon-chip in the Xtal mode?
    If possible, please give us the simple answer to this question at first.

  • Because of the holidays, TI E2ETm design support forum responses may be delayed from Dec. 22 through Jan. 2. Thank you for your patience.

  • Susumu,

    So, to be clear - you have 18 pF total capacitance. Is this how much the XTAL datasheet calls for, or does the datasheet call for 10 pF total capacitance?

    The varactor (variable capacitor) is able to be swung from 0.3x to 1.3x the selected load capacitance value by adjusting the tuning voltage. 1.3xCLon-chip is with 0V as the tuning voltage, as is shown by Figure 5 in the application note.

    If you remove the 10-pF capacitance and only use the on-chip capacitance, is the pulling range increased?
    Thanks,

    Kadeem

  • Thank you for your reply.
    I do appreciate your repeated explanations.

    The datasheet of the XTAL we use calls for 10pF total capacitance.
    So I set 8pF to the internal capacitance.
    And we use only the internal capacitance.
    There is no external capacitance from the beginning.

    In this situation, the pulling range is about 100ppm.

    What I want to know is the setting of the coefficient for CLon-chip at the Xtal mode (INCLK=00).
    Not at the VCXO mode (INCLK=01).

  • Susumu,

    In the XTAL mode, the capacitance is fixed at external capacitance + parasitic board/trace capacitance + internal register-configured capacitance, CLon-chip. The coefficient for CLon-chip in XTAL mode is fixed at 1. R5[7:3] sets this value.

    Thanks,

    Kadeem

  • Thank you for your reply!!

    >> The coefficient for CLon-chip in XTAL mode is fixed at 1.

    Thank you for your comment. This is the answer I want.
    However, we think it contradicts our experiment I sent at first.

    >> ・Measurement result
    >> In Xtal mode (Vctrl=1.8V) 26.9992MHz
    >> In VCXO mode (Vctrl=0 V) 26.9992MHz
    >> In VCXO mode (Vctrl=0.9V) 27.0011MHz
    >> In VCXO mode (Vctrl=1.8V) 27.0019MHz
    >>
    >> ・Fixed conditions
    >> CDCE925 external reference crystal 25.000MHz
    >> CDCE925 output clock frequency setting 27.000000MHz
    >> CDCE925 internal load capacitance register setting 8pF
    >> * Other than OFFSET=01h, bit3-2 INCLK settings are not changed.

    We think that the output frequency at Xtal mode should be the same as the output frequency at VCXO mode (Vctrl=0.9V).
    Because we understand that "Vctrl=0.9V" is the situation for the coefficient for CLon-chip is 1 in the VCXO mode.

    Is this correct?
    Please teach why the output frequency at Xtal mode is the same as the output frequency at VCXO mode (Vctrl=0V).

  • Susumu,

    Apologies for the confusion. Xtal mode can be understood as VCXO mode when Vctrl = 0V, as seen in those two cases having the same output frequency. The architecture used during VCXO mode causes a different frequency behavior to be exhibited when the same load capacitance is applied, resulting in the difference between Xtal mode and Vctrl = 0.9V

    Best,

    Cris

  • Thank you for your reply.

    I understood that "Xtal Mode" can be understood as "VCXO mode with Vctrl=0V".
    This conclusion matches our experiment.


    I think this is last question.
    Please teach actual equation for "CL" at Xtal mode.

    The "VCXO Application Guideline for CDCE(L)9xx Family" says, CL = a x CLon-chip + Cs ( 0.3 < a < 1.3 : a is determined by Vctrl).

    We understood that this is actual equation for "CL" at VCXO mode.

    Please teach the equation of the CL at the Xtal mode.
    We concern that "CL = 1.3 x CLon-chip + Cs" at Xtal mode.


    Thank you.

  • Susumu,

    I am discussing this with the designer. Please expect a response by EOD Monday.

    Thank you,

    Cris

  • Susumu,

    We are looking into the design to determine the coefficient for the Xtal load capacitance. However I do want to reiterate that the architecture for Xtal mode is very different from VCXO mode. So upon even having the same CL, these two modes will almost always have a different frequency response. 

    Best,

    Cris

  • Susumu,

    Based on further testing and discussion, the coefficient for CL in Xtal mode does seem to be 1.3. 

    Best,

    Cris

  • Cris,

    Thank you for your answer!!
    We'll adjust by using the coefficient of 1.3 at the Xtal mode.

    Best regards,

    Susumu Yukawa