Hello:
I am having issues setting register values in the CDCE62002 EVM Software. Specifically, I cannot setup the device to ensure PLL lock. I have a 10MHz input signal and wish to decrease the phase jitter on a 20MHz output signal.
Attached is a screen shot with the current settings.
What are the correct settings to enable PLL lock? What are the correct SPI settings? Here are my current Reg 0 -- 2 settings:
Register 0: 647800e0; Register 1: bd002001; Register2: 20003812
Thanks!
Kerri