• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 493 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK05318B: PLL filter configuration

LMK05318B: DLL not locking

Andrea Pastega
Prodigy 150 points
Part Number: LMK05318B


Hello,

please refer to my previous related post, which has been closed without an answer.

I'm trying to employ DLL to lock PLL1 to an external reference on PRIREF or SECREF.

Up to previous post, I tried with a sine 10MHz on PRIREF, DLL seemed to lock sometime, but not in stable way.

I sent registers dump for TI review.

Given that there was concern about sinewave having too high risetime, now I'm also trying with an LVDS 10MHz signal connected to SECREF.

I configured SECREF input for AC coupling, 50mV hysteresis.

I selected value 0E for register R48 (STAT0_SEL = SECREF Monitor Divider Output, div-by-2") in way to monitor what is actually received at SECREF.
There's no waveform on STAT0, that means no signal received?

Please note that SECREF_VALSTAT = 1, but DLL doesn't lock. 

What is the correct configuration for LVDS input?

Thanks

Andrea

  • 0
    TI__Genius 16765 points

    Hi Andrea,

    I'm not sure why it got closed, sorry about that!

    1. Could you please share your schematic snippet?
    2. Are you using the LMK05318BEVM (TI  eval board)?

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Prodigy 150 points

    Hi Jennifer,

    good to see you again.

    LMK05318B_inputs.pdf

    I attached a schematic of the inputs to the LMK05318B. As from previous messages, we are using a custom board.

    As you can see, PRIREF is connected to a coaxial connector, we tried to use the sinusoidal 10MHz reference here.

    It almost works, but DLL never locks completely, holdover doesn't work as tuning word is never stored. 

    SECREF is connected to FPGA_REF differential LVDS output. In this way I can use FPGA to generate a squarewave 10MHz signal for tests.

    I'm trying to use STATUS0 and STATUS1 pins to check if these references are received correctly, configuring R48/R49 to 0x0D/0x0E.

    LVDS 10MHz on SECREF gives R411 SECREF_VALSTAT at 1, but on STATUS1 signal is constant low. DLL doesn't lock and there's no synchronization.

    Andrea

  • 0 in reply to Andrea Pastega
    TI__Expert 3135 points

    Hi Andrea,

    Looks like the previous thread got locked, not sure why. But I'm able to get back the dump register file to review. Just skim through the schematic and it looks fine. Let me duplicate the issue with the dump file on my bench and check on it.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 150 points

    Hi Riley,

    thanks for the help.

    The DLL is a delicate part of the system. Almost all related registers on the manual are marked as "RESERVED" so it's not possible to understand very well how it works. Beside this, the only way to determinate the value is using TICS, but in our computers the part related to DLL doesn't works (I mean the Matlab script is not executed as expected, simply hangs forever).

    Given that we need to develop a control API for the LMK, which runs on custom board with an ARM core, and that because of flexibility reasons we can't use a static configuration (e.g. written in EEPROM), it would be very important for us to understand exactly how the whole chip works. 

    Could it be possible to receive a complete documentation, I mean with all registers described well? This surely will help a lot also in debug.
    If it is required, we could sign an NDA (maybe we already signed for other TI products).

    Please let me know.

    Thanks

    Andrea

  • 0 in reply to Andrea Pastega
    TI__Expert 3135 points

    Hi Andrea,

    Please take a look at the programming guide for LMK05318B LMK05318B programing guide.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 150 points

    Hi Riley,

    of course I did!

    Problem is: sections related to DLL are not described at all, or all bits of several registers are marked as RESERVED. Debug is quite difficult if you can't understand well what you are doing, unfortunately "already cooked" configuration form TICS has some weak point...

    Any help in this direction?

    Andrea

  • 0 in reply to Andrea Pastega
    TI__Expert 3135 points

    Hi Andrea,

    The hex registers from "LMK05318B_dump.txt" showing that DPLL is tuning BAW VCO at 2550MHz hence BAW_LOCK = 0 (R80 0x005000).

    With 10MHz PRIREF/SECREF, to tune BAW VCO at 2500MHz, the DPLL settings would be:

    DPLL_REF_FB_PRE_DIV = 5

    R304 0x013003

    DPLL_REF_FB_DIV = 25

    R305 0x013100
    R306 0x013200
    R307 0x013300
    R308 0x013419

    DPLL_REF_DEN = 2^40

    R314 0x013A00
    R315 0x013B00
    R316 0x013C00
    R317 0x013D00
    R318 0x013E00

    DPLL_REF_NUM = 0

    R309 0x013500
    R310 0x013600
    R311 0x013700
    R312 0x013800
    R313 0x013900

    Your setting has R309 0x013580 which sets DPLL_REF_NUM = 549755813888 => BAW VCO = 2550MHz.

    Also, in APLL2 settings, you're using divider 306 + 9/10.

    However, R136 & R138 (PLL2_NUM) are reserved in values:

    R136 0x008809
    R137 0x008900
    R138 0x008A00

    -> this sets PLL2_NUM = 589824

    R136 0x008800
    R137 0x008900
    R138 0x008A09

    -> this sets PLL2_NUM = 9

    Similarly, R333 & R335 (PLL2_DEN) are reserved in values. The correct settings to have PLL2_DEN = 10 would be:

    R333 0x014D00
    R334 0x014E00
    R335 0x014F0A

    Hope this helps.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 150 points

    Dear Riley,

    you are right about R309, it was a typo indeed.

    With corrected value I managed to lock to 10MHz LVDS reference provided on SECREF. 

    I verified this lock condition comparing SECREF to OUT7 (also 10MHz, derived from APLL1), after lock has reached, the two waveforms don't roll each other.

    However, checking lock registers, still something is not fine:

    Status @ 50: 0x00
    BAW_LOCK: 0
    Status @ 0D: 0x0040
    LOS_FDET_XO: 0
    LOS_PLL2: 0
    LOS_PLL1: 0
    LOS_XO: 0
    LOPL_DPLL: 0
    LOFL_DPLL: 1
    HIST: 0
    HLDOVR: 0
    REFSWITCH: 0
    LOR_MISSCLK: 0
    LOR_FREQ: 0
    LOR_AMP: 0
    Status @ 19B: 0x08
    PRIREF_VALSTAT: 0
    SECREF_VALSTAT: 1

    BAW_LOCK, which is 1 when DLL is disengaged (lock to local XO), goes to 0 when SECREF is enabled and DLL begins to lock. This could be correct, because external 10MHz on SECREF is not very accurate.

    SECREF_VALSTAT bit goes to 1, so SECREF is validated

    LOPL_DPLL goes to 0, so DLL is phase-locked.

    However LOFL_DPLL never goes to 0, thus frequency tuning word is never saved, and in case SECREF reference is disabled, APLL1 just goes to same frequency as with DPLL disabled (tuning word 0).

    This is the same condition I had with the sinewave 10MHz connected to PRIREF, which was considered as not very good because of the excessive rise time (see previous posts).

    So actually DPLL holdover function still doesn't work.

    What could be the reason why DPLL doesn't lock in frequency?

    Thanks

    Andrea

  • 0 in reply to Andrea Pastega
    TI__Expert 3135 points

    Hi Andrea,

    For DPLL frequency lock, you might want to increase lock detect threshold. This can be done through GUI page, increasing Lock ppm and Unlock ppm to higher numbers then once it locks, you can decrease to smaller thresholds.

    Or you can change R321 and R331. Note that increment is 0.1ppm for hex value

    -Riley