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LMK5C33216: SYNC only APLL2

Jonathan Kolbrak
Intellectual 490 points
Part Number: LMK5C33216

Hello,

I have clocks running on APLL1 (no DPLL), that I do not want reset during a SYNC event.  

Step 4 above says to write R23[6] which will reset all functions. Is it possible to execute the same steps and have a SYNC event for only APLL2 without causing APLL1 to reset?  Can writing to APLL2_SWRST perform the same function but for just APLL2?

Jon

  • 0
    TI__Genius 12435 points

    Hi Jon,

    1. Can you share your intended .tcs file?
      1. I would like to understand if you're cascading the APLLs or if each APLL is sourced directly from the XO input. This will help me advise whether APLL2_SWRST is appropriate.
    2. APLL2_SWRST issues the SWRST for only APLL2 which restarts the APLL2 calibration. APLL2_SWRST does not guarantee edge alignment between outputs which is what SYNC does.
    3. If you only want outputs from APLL2 to be affected by a SYNC event, you can disable the non-APLL2 SYNC_EN and any non-APLL2 output SYNC_EN. For example:
    4. By the way, are you using the LMK5C33216 or LMK5C33216A? The A version is latest silicon with jitter and output driver improvements.

    Regards,

    Jennifer

  • 0
    Intellectual 490 points

    LMK5C33216.tcs

    Hi Jennifer,

    I'm attaching the .tcs file.  Each APLL (1 and 2, three is unused) are connected to the XO.

    We are using the non 'A' version for now but will look at the 'A' version for the next revision.

    Based on your point 3 above I may have had a SYNC EN set for PLL1 so that could be my issue.

    Jon

  • 0 in reply to Jonathan Kolbrak
    TI__Genius 12435 points

    Hi Jon,

    Have you been able to test further? This seems to be the case if you had SYNC enabled for PLL1, then all PLL1 outputs will be impacted by a SYNC_SW event.

    Regards,

    Jennifer