Dear Sir or Madam,
I want to make the fixed deterministic phase between clock outputs in all of the multi-boards.
First, please see the following my multi-boards configuration.
Unfortunately, in my testing experience, the phase relationship between the output clocks of FM boards is always changed on each power-up.
So, In order to get all of these multi-boards to work well, I have to do an alignment of the phase of the FM boards at every power up.
As you know, it's really unreasonable to adjust the phase at every time.
I would like to know how to get a fixed phase and synchronous phase between all FM boards, even after power off and on.
Please check the resistor map and programming sequence to achieve the synchronous divider of Device Clock Output as follows.
R0 (INIT) 0x000090 R0 0x000010 R2 0x000200 R3 0x000306 R4 0x000463 R5 0x0005D1 R6 0x000670 R12 0x000C51 R13 0x000D04 R256 0x010010 R257 0x01010A R258 0x010200 R259 0x010340 R260 0x010420 R261 0x010500 R262 0x010601 R263 0x010711 R264 0x01080A R265 0x01090A R266 0x010A00 R267 0x010B40 R268 0x010C20 R269 0x010D00 R270 0x010E01 R271 0x010F11 R272 0x011010 R273 0x01110A R274 0x011200 R275 0x011340 R276 0x011400 R277 0x011500 R278 0x011601 R279 0x011711 R280 0x011810 R281 0x01190A R282 0x011A00 R283 0x011B40 R284 0x011C00 R285 0x011D00 R286 0x011E01 R287 0x011F11 R288 0x01200A R289 0x01210A R290 0x012200 R291 0x012340 R292 0x012420 R293 0x012500 R294 0x012601 R295 0x012711 R296 0x01280A R297 0x01290A R298 0x012A00 R299 0x012B40 R300 0x012C20 R301 0x012D00 R302 0x012E01 R303 0x012F11 R304 0x013001 R305 0x01310A R306 0x013280 R307 0x013340 R308 0x013430 R309 0x013500 R310 0x013601 R311 0x013711 R312 0x013801 R313 0x013910 R314 0x013A03 R315 0x013BE8 R316 0x013C00 R317 0x013D08 R318 0x013E03 R319 0x013F01 R320 0x01408D R321 0x014100 R322 0x014200 R323 0x014310 R324 0x01443F R325 0x014568 R326 0x014608 R327 0x01470C R328 0x014802 R329 0x014902 R330 0x014A00 R331 0x014B06 R332 0x014C00 R333 0x014D00 R334 0x014EC0 R335 0x014F7F R336 0x015001 R337 0x015102 R338 0x015200 R339 0x015300 R340 0x015478 R341 0x015500 R342 0x015601 R343 0x015700 R344 0x015896 R345 0x015900 R346 0x015A96 R347 0x015BD4 R348 0x015C20 R349 0x015D00 R350 0x015E1E R351 0x015F3B R352 0x016000 R353 0x016101 R354 0x016240 R355 0x016300 R356 0x016400 R357 0x01650C R361 0x016958 R362 0x016A20 R363 0x016B00 R364 0x016C00 R365 0x016D00 R366 0x016E13 R371 0x017310 R375 0x017700 R386 0x018200 R387 0x018300 R358 0x016600 R359 0x016700 R360 0x01687D R1365 0x055500
Programming Sequence tor achieving the Sync of divider.
** 2.5MHz SYSREF is continuously delivered to the clkin0 from other LMK04832 on the main board.
(1) Set from 0x14311 to 0x14391 (SYSREF CLR)
(2) Set from 0x1443F to 0x14400 (SYNC_DISx and SYNC_DISSYSREF)
(3) Toggle the SYNC signal for at least the duration of one cycle of the 2.5MHz SYSREF.
(4) Set from 0x14400 to 0x1443F (SYNC_DISx and SYNC_DISSYSREF)
(5) Set from 0x14391 to 0x14311 (SYSREF CLR)
** It seems that difference phase between sysref and device clock is changed after doing this sequence.
In my opinion, if each of the dividers is reset simultaneously to the SYSREF signal - rising edge? or falling edge? - it's always right to have a fixed phase relationship between SYSREF and the device clock, isn't it?
But it's always changed the phase difference between SYSREF and the device clock randomly after doing every this programming sequence.
I'm waiting for your kind reply.
Thank you,
Best Regards,
