LMK04828: How to set JESD clock?

Daniel,

Could you send me your .tcs file?

Regards,

Will

Hello William,

Attached is my tcs file.

Thanks

Best regards.

7382.lmk04828.tcs

Daniel,

I will get back to you by next Friday.

Regards,

Will

Daniel,

Thank you for your patience. 

In regards to the schematic, here is feedback:

• does DNL mean the part will not be placed?
• If you are using 50 ohm traces you should add a 50 ohm termination before the AC coupling cap.
  
  • 
• Because you are not using a PLL, you do not need any loop filter components.  Can you explain why you placed loop filter components on  CPOUT2?
• I understand the 120 ohm termination resistors on DCLKOUT2, but I am a little confused at how you came up with your termination resistor values for your other outputs 0,1,3,12.  Could you explain?
  • 

In regards to the ticspro, here is my feedback:

• What is the type of SYSREF signal that you are desiring? It was not clear from your SYSREF_MUX Selection.
  • 
• Can you elaborate how you want to sync your signals and then what kind of SYSREF signal that you will require. Ex. How many pulses do you need?
• CLKIN_SEL0 and CLKINSEL_1, if you are using them as an output which it looks like you are from your schematic should be configured as such.
  •  

Regards,

Will

Hello Will, 

Thank you for your review.

In regards to the schematic, below is our answer.

1. Yes, DNL means Do Not Load, parts are not soldered on PCB

2. 50R at input, we could try adding an external 50R on existing PCB. 

3. PLL loop filter components are reserved on board just in case of use in future. And we do not want to use internal PLL on existing project for the time being. 

4. LMK04828 DS shows 560R differential res for LVDS output with internal receiver termination on page 106. And two 280R resistors to GND contributes 560R in differential. 

5.LMK04828 DS shows 100R differential res for LVDS output with external receiver termination, two 200R resistor to GND makes 100R in differential.

In regards to the ticspro, below is our answer.

1. For SYSREF, we prefer use continuous.

2. For CLKIN_SEL0, we do not use. For CLKINSEL_1, we prefer use as input 2.5G, bypass/divide for DCLKOUT0/SDCLKOUT1 to FPGA, bypass/divide for DCLKOUT2/SDCLKOUT3 to DAC38J82.

Attached is our new tcs file.

lmk04828_2nd.tcs

By another way, based on our schematic, would you please help provide the settings for LMK04828 and DAC38J82 (without any using restriction)? 

We hope we can run a sinewave demo base on your settings.

Thank you

Best regards

Daniel

Daniel,

The team is out of office for the US holiday, please expect a response by tomorrow.

Thanks,

Kadeem

Daniel,

Sorry for the delay.   I understand, all your points make sense to me.  A note from the data sheet about continuous mode that I would caution you on:

Continuous operation of SYSREF is not recommended, due to crosstalk from the SYSREF clock to device clock. JESD204B is designed to operate with a single burst of pulses to initialize the system at startup, after which it is theoretically not required to send another SYSREF, because the system continues to operate with deterministic phases. If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or SYSREF from the OSCout pin, to minimize crosstalk.

I will review your tics config and get back to you tommorow.  Do you also need support generating programming for the DAC38J82?

Regards,

Will

Will,

Thanks for your notice.

Our first target is run a sinewave demo to our customer. It is very helpful that you can provide more reasonable settings or usage.

Next we can modify to meet customer usage.

Yes, we also need DAC38J82 support. I think the default register value of DAC38J82 is enough for sinewave demo, but I am not sure about this.

I think clocking is the first priority, we need generate correct clocking then need TI support DAC38J82.

it is helpful if you or someone can support DAC38J82.

Thanks.

Daniel

Daniel,

For support in configuring these two devices together it might be helpful to look at the DAC38J82 EVM and its documentation as this uses the LMK04828 to clock the DAC.  I will follow up on Monday with more information. 

Regards,

Will

Hi Will,

I have reviewed some DAC38J82 EVM documents and GUI software. 

Currently, I have one questions.

If I select External clock. what frequency should I input? 

Thanks

Daniel

Daniel, 

I am adding a apps engineer from the DAC team to support as I am not familiar with the software. 

Regards,

Will

Hi Daniel,

Sorry for the delay, we will answer this by tomorrow EOD.

Thanks,

Rob

Daniel,

Can you share what mode you are wanting the DAC to operate under? This includes the overall DAC sample rate and interpolation factor. Interpolating means you provide a less amount of data into the DAC but the DAC still outputs the data accurately. The tradeoff is the higher interpolation factor, the lower the useable bandwidth of the signal you are capable of providing into the device. In the image you posted, you are showing 312.5MSPS input rate and interpolation of 1, which means the DAC output will match the DAC input data rate of 312.5MSPS.

First, you need to decide what useable bandwidth you require. If you need to send a tone that is 20MHz wide for instance, you need to supply at least twice this amount into the DAC inputs to avoid aliasing. This for instance could mean you desire a DAC input data rate of 50MSPS. Next you will choose an interpolation factor which will directly affect the sample rate of the DAC. If you choose interpolation by 2, the DAC must receive a 100MHz clock input. If you choose interpolation by 16, then the DAC will operate at a sample rate of 1600MSPS and requires a 1600MSPS clock.

Please see Table 10. DAC38J82 Speed Limits of the DAC38J82 datasheet for available options of interpolation rate and data rate/sample rate.

Thanks, Chase

Hi Chase,

Thanks for your response. 

I did some research and study this theory. Also try some configurations. But it is not work now.

First, we need a demo for our customer. And my target is sample rate = 312.5M, interpolate x1, combined with TIJESD204-IP example design (64 points sinewave), I expect there is a 4.88M sine wave output. But nothing actually.

Below is my steps,

1. On DAC3XJ8X GUI, Select External Clock, Select DAC38J82, Input 312.5MSPS, input 8 Serdes Lanes, input 1 interpolation.

2. At simulation mode, Click Program LMK04828 and DAC3XJ8X. There will be whole register value shows in log window.

3. Follow the whole register value as my system configuration.

4. Inside TIJESD204-IP example design (Xilinx), change to correct LMFS and K. Also change the Serdes data rate to 1.5625GHz

5. Using VIO and ILA to see the tx data already send to TIJESD204-IP. But no wave from DAC output.

Also I try to modify some register value, still not work.

Now I focus on TIJESD204-IP example design, maybe something I am not noticed.

If you have some advice, please help.

Thanks

Daniel

Hi Daniel,

Thanks for the good detailed info. Since you are using TI-204C-IP, let’s start at the beginning. Does the PLL status show as 0x3 when you toggle the master_reset vio from 0 to 1?

Thanks, Chase

Hi Chase,

Thanks for your quick response.

Yes, I have got 0x3 of QPLL status.

Below is my screen short of VIO and ILA.

Thanks, Daniel