Hi,
Could someone provide me with LMK04828B and LMX2594 configuration files for the following specs?
The LMK clock out is 156.8 MHz and the reference clock to LMK is 204.8 MHz. The Sysref clk required is 7.84 MHz.
The ADC sample rate is 1.2544 GSPS.
Thank you.
Hi Mazbeen,
In order to get a higher PLL2 fpd and therefore higher PLL2 performance, you may consider to use a 125.44Mhz VCXO in PLL1.
We can get both 156.8MHz clock and 784MHz SYSREF clock.
Not using PLL1 is still ok, but PLL2 fpd will be confined to 51.2MHz.
Using the LMX2594 to generate these clocks seems not a good idea as fpd is quite low.
LMX2572 is a better choice over LMX2594, fpd could be higher.
