LMX2820: Time to stable output after toggling chip enable

I am considering an application that would use the LMX2820 as follows:

1. Power is applied to the LMX2820.
2. Reset and configure all registers are configured, with instant calibration
3. Set to some frequency
4. Drive chip enable low
5. Drive chip enable high when we need its output

What is a bounding time from driving the chip enable high in step 5 to having a valid output? I assume that the same VCO cal and PLL lock time is present, but I'm wondering about other power-up/enable delays. E.g. the "Initialization and Power-Sequencing" section of the datasheet alludes to a 10 ms wait for LDO stabilization after initial programming. Is that time also present after chip enable?

I've measured this on the bench and saw several 100 us, but I would like to confirm what to expect across many units. If this behavior is not expected to vary significantly from unit-unit then I can just use lab measurement.

For context, the primary reason for using chip-enable like this is to eliminate RF energy at the output entirely, as the ~40 dB mute is not sufficient for this application. I am definitely interested to know if there are better ways to accomplish that goal with the LMX2820.