CDCM6208: What is the prop delay spec on the primary input to the Y5 output in bypass mode?

Mike,

This is not a parameter that we have a specification for.

Thanks,

Kadeem

Kadeem,

I am aware that is not specified in the datasheet.  I am hoping you can provide more information.  Is there data from the chip simulation?

Mike

Mike,

I can check this with the design team, but the server that contains the design files for this chip will not be up again until 3/4 at the earliest.

Thanks,

Kadeem

Kadeem,

I can wait a couple weeks for this, I will pad the measured value some for now and hope to have a more definitive number when you get access to the server.

Thanks for your help.

Mike

Kadeem, 

Do you have access to the server now?  Can you try to get the delay value range?

Thanks,

Mike

Mike,

I finally found some old validation data, these are the test conditions: VDD_Yx_Yy = 1.71 TO 1.89V, 2.375V TO 2.625V, 3.135V TO 3.465V, TA = -40C TO 85C, CDCM6208V1, fVCO=2.5GHz; PS_A=4/5/6 and CDCM6208V2, fVCO=3GHz; PS_A=4/5/6

Propagation delay, as related to the PS_A frequency, is estimated to be between 9x to 12x the period 1/f_PSA. This is on the order of tens of picoseconds.

Working to see if one of the designers has bandwidth to look into this discrepancy while I investigate on the bench - the servers should be back online now.

Thanks,

Kadeem

For the bypass path, how is the prop delay a function of the divider frequency?  It just goes through two buffers.  No flip-flops....  

Kadeem,

I see about 1ns when probing at the blocking caps I have very close to the part - less than 5mm away.  I am suspicious of your 4ns value.

This output is driving an FPGA and clocking in other synchronous signals.  I need the min and max so I can set up the timing constraints  the FPGA.  

Regards,

Mike