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LMK1C1102: Clock gating

Ben Campbell
Prodigy 50 points
Part Number: LMK1C1102
Other Parts Discussed in Thread: SN74AUC1G74

Dear TI E2E,

I have a slightly odd requirement that I have not been able to find an obvious solution to. I wondered if someone had a nice idea how to solve it please!?

I have a very low noise, CMOS, 200MHz clock, that I would like to distribute. I only want to distribute certain edges. For example, I would like to output every 8th edge, so the output would be a single 2.5ns pulse every 8 cycles. The actual use case has a more varied Nth edge requirement. 

I can see the LMK1C1102 has a gate/output-enable pin, but the datasheet says there is maximum 5 cycles output enable/disable time (see specs t1G_ON and t1G_OFF). So it wouldn't work, because as I understand it, I'd have to enable, wait 5 cycles for the first edge, disable, wait another 5 cycles. So I'd get 5 cycles outputted. Is my understanding correct?

One other solution I can see, is to use a high speed flip-flop, like SN74AUC1G74. However, TI don't measure additive jitter for logic (ref https://e2e.ti.com/support/logic-group/logic/f/logic-forum/810935/sn74auc2g32-jitter-of-sn74auc-family). I cannot use a part without any jitter guarantees.

Thank you for any suggestions!

Ben

  • 0
    TI__Genius 10975 points

    Hi Ben,

    What are your jitter requirements for this solution? Apart from the pulse description you gave and it being a CMOS outputs, do you have any other requirements for your system?

    Also, why do the requirements listed above matter, especially for the pulse requirements? What application is this for and what are you clocking? Thanks!

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 50 points

    Hi Andrea, thanks for replying.

    The jitter requirements is <1ps RMS (12 kHz - 20 MHz). I'm clocking a proprietary RF circuit, sorry I can't explain more in public. 

    Why do they matter? I was trying to explain my conundrum - how to selectively gate a clock, without adding significant jitter (or using a part whose additive jitter is unspecified). I could not find any gated clock buffers which could gate a single clock pulse. I was also questioning if my understanding of how the gate on LMK1C110x worked was correct.

    Thank you!

  • +1 in reply to Ben Campbell
    TI__Genius 10975 points

    Hello Ben,

    Your understanding about the LMK1C is correct. I don't believe any of our CMOS devices will behave differently as most of them have this latency between turning the enable on/off and the output being enabled. I'll check with my team to see if they have any ideas.

    Regarding your questions with the logic device SN74AUC1G74, I recommend you create another post only with that device as that question pertains to another team that'll be able to better answer your questions about that device. If this device does work do let me know!

    Best,

    Andrea