Hi:
I'm trying to understand the requirements to get a deterministic skew from input-to-output on an LMK04610 using PLL2-only mode. The overall clocking architecture we have is pretty simple, in that the output clocks needed are just integer multiples of the output (15.625M -> 125M, 375M, 187.5M).
My first thought was that I needed to use the zero-delay mode using feedback from CLKout5/CLKout6 on an LMK04610, but I saw a post here that suggested that so long as the PFD is the GCD of the input and output clocks - which would just mean that the PFD needs to be 15.625M - that the skew is deterministic anyway.
Is this correct (it would open up a clock output if so)? I would guess that this means that SYNC resets the PLL N divider as well as the output clocks dividers?
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A related question is if we do use zero-delay feedback (say, by adding CLKout5 at 15.625M) and we then have a *fractional* output (say 7.8125M, so fout=(1/2)fin) - if we then issue a SYNC to multiple LMK04610s during the same 15.625M period, would the 7.8125M outputs have deterministic phase between the two devices?
It seems like they should, because the zero-delay mode means the phase of the 15.625M input and output must be identical and the SYNC says that it forces the outputs to all share a common rising edge. Is this understanding correct?
