LMK04832: Unlock previous thread

Hello Brad,

I'm unsure how to unlock a thread, in the meantime while I figure it out, I have copied Derek's response below:

"The charge pump on LMK04832 PLL1 is maximum 3.3V, so if you need to pull at the top of the range you're going to have issues. You may need to use an active op-amp circuit to gain up the charge pump signal by a factor of 5/3.3 to access the full pull range.

The pull range (or more precisely, the VCO gain) will definitely have an impact on the loop stability as well. The default PLL1 loop filter, for example, is designed for a 2.5kHz/V gain slope, resulting in the following 40Hz, 41° phase margin loop filter:

Just to demonstrate the issue, I now set the gain 1000x lower, to 2.5Hz/V. I change nothing else. My new loop bandwidth is 0.5Hz and my phase margin is 4.5°.

You must design your loop filter with the VCO gain in mind. PLLatinum Sim can help with this, offering a way to set the Kvco gain characteristic for your oscillator.

1. Select LMK04832, PLL1. Set feature level to at least intermediate. You probably also want to adjust the graph settings under the phase noise tab, to capture the full range of offsets you want to look at.
2. Set up the PLL portion of the circuit how you want - you can leave loop filter at default for now. Set the charge pump gain in advance; you likely want it as high as it can go if you want a reasonably-valued loop filter. You probably want the phase detector frequency as high as you can make it as well, to minimize the PLL1 FOM noise contribution.
3. I recommend importing a VCO phase noise trace; any comma, space, or tab-separated value file with column 1 as carrier offsets and column 2 as phase noise in dBc/Hz will work as an importable phase noise trace.
4. Set Kvco to the value computed for your VCOCXO. Observe that the bandwidth and phase margin are very small.
5. On the Filter Designer tab, set the desired loop bandwidth and phase margin. Loop bandwidth is up to you, whatever value is reasonable, though I recommend less than 50Hz. Phase margin you probably want 40° or more. Click Calculate Loop Filter.
6. If the actual values or the proposed loop filter components don't make sense, keep playing with Fpd, Kpd, Loop Bandwidth, and Phase Margin until you get the desired results. There's an annoying bug I just noticed where setting Kpd or Fpd resets Kvco to some other value, so if you change Fpd or Kpd make sure to reset Kvco to the correct value before proceeding."

Let me know if you have any other questions in the meantime.

Best,

Andrea

Quick sidebar question:

If my VCXO only has +/- 4Hz pullability, am I constrained to 8 Hz loop bandwidth?

Not necessarily. Even if you can only change by ±4Hz, you may still be able to jump from +4Hz to -4Hz much faster than 8Hz loop bandwidth.

The tuning range of the VCXO sets Kvco in PLLatinum Sim, and while loop bandwidth is impacted by Kvco, it is also impacted by Kpd, Fpd, and loop filter coefficient values. If you have a high enough Fpd and Kpd value, and you select loop filter coefficients that do not significantly limit the bandwidth, higher bandwidths are possible. As an example, I tested a 10MHz reference and 100MHz VCXO with 2Hz/V tuning range in PLLatinum Sim, and I can see that at maximum gain and certain loop filter values I can get 20Hz loop bandwidth.

However, you might run into an effect that is NOT modeled by PLLatinum Sim: the modulation bandwidth of the VCXO. Even if you can change the voltage at the tuning port very quickly, in practice a narrowband VCOCXO can't respond as quickly to tuning port modulation. The Crystek CVHD-950 VCXO on the LMK04832EVM has >10kHz modulation bandwidth; sampling some VCOCXOs on various distributors, I see values of 1kHz or less very commonly, some pushing down to 100Hz or lower. The rolloff from the modulation bandwidth will add another pole to the system, which can impact stability and loop bandwidth if the pole is too close to the other poles set by the PLL and loop filter characteristics. Try to keep the loop bandwidth at least a factor of 10 smaller than the VCXO modulation bandwidth if possible.