LMK00301: JitterADD

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Part Number: LMK00301

Under the conditions of LVPECL, Vcco=3.3V, CLKin=156.25MHz,
JitterADD (Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz) of LMK00301 is typ:54fs, max78:fs.
Under the conditions of LVDS, Vcco=3.3V, CLKin=156.25MHz,
JitterADD (Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz) of LMK00301 is typ: 70fs, max: 90fs.
However, we need a jitter of 8fs or less to meet our specifications.
Is there a clock divider with LVCMOS input, LVPECL output x1, and LVDS output x5 with jitter of 8fs or less?

7 months ago

0 William Pfennigwerth 7 months ago

TI__Expert 8231 points

Hi,

Firstly, to check your jitter requirement I will need to know what the integration bandwidth and frequency the jitter specification of 8fs or less is measured at.

Regards,
Will

0 ?? ?? 6 months ago in reply to William Pfennigwerth

Prodigy 40 points

Hello William,

Thank you for your reply.

Integration bandwidth:20MHz.

Input and output frequency:110MHz.

Best regards.

0 William Pfennigwerth 6 months ago in reply to ?? ??

TI__Expert 8231 points

Hello,

Thank you for the information. The integration bandwidth is usually a range, like 12kHz to 20MHz or 2MHz to 20 MHz. Could you clarify?

Regards,

Will

0 ?? ?? 6 months ago in reply to William Pfennigwerth

Prodigy 40 points

Hello William,

Thank you for your reply.

The Integration bandwidth is 12kHz to 20MHz.

Best regards.

+1 William Pfennigwerth 6 months ago in reply to ?? ??

TI__Expert 8231 points

Hi,

We do not have a solution that meets all your requirements. The closest thing I can recommend is the LMK01000 which can accept single ended inputs and has 3 LVDS and 5 LVPECL outputs, although at a higher jitter (LVPECL @ 200 MHz 100Hz-20MHz is 65fs) so not a direct comparison.

Regards,

Will

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LMK00301: JitterADD