CDCM7005-SP - Clock inputs synchronization information

michael grandjean

Hello,
Having the M divider = N divider and P divider = 1 as requirement: what happens if the pri_ref = 6.25 MHz and VCXO = 100 MHz?
The matter is that 6.25 MHz / M is different from 100 MHz / (N * 1): keeping in mind than 1 <= M = N <= 1024 is a required condition!
This condition cannot be simulated with the TI PLL Sim tool version 1.2!
Is this condition a nominal working condition of the device?
From what I've read, it looks more like both frequency should be equal at the input of the PFD block! Is that correct?
Thanks for some information

over 14 years ago

0 Julian Hagedorn over 14 years ago

TI__Mastermind 20900 points

Hello Michael,

the settings that you are describing will never work. In general you need to have the same frequency at the PFD to lock the whole PLL. So you have to make sure with the M, N and P dividers that you have the same frequency there.

For example:

Ref input = 6.25MHz; output = 100MHz; VCXO= 100MHz; M=N=1 => this means that you have to select FB_MUX=16.

Best regards,

Julian

0 michael grandjean over 14 years ago in reply to Julian Hagedorn

Prodigy 20 points

Ok. Thanks for your information.

Clock & timing

Clock & timing forum

CDCM7005-SP - Clock inputs synchronization information