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LMK04832: CLKIN0/1 PLL1 Reference Input 100MHz

KLN
Intellectual 320 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMK04828,
Hi,
We have a question on LMK04832/LMK04828, 
In one of the new projects that we are working on, LMK04832 will be used to generate the clock to Xilinx RFSoC.
  • The customer mentioned the option for inputting External Clock, hence we are thinking of feeding external clock input to CLKIN1 of LMK04832
  • The External Input clock will be 100MHz with good phase noise of -150dBc/Hz
  • On-board reference clock input to CLKIN0, which is also a 100MHz OCXO part: KLNBNTE100MFNFCAB
  • OSCIn Input will also be 100MHz VCXO
     
Our query is that,
  • Is it okay to feed the PLL1 Reference clock of 100MHz
  • Is the PFD of PLL1 will have any issues? Due to high R & N-divider
  • What value of PFD, Do you suggest for this case? As Fpd1 is 40MHz for PLL1
I would appreciate your suggestions on this case.
 
Note: In our previous application, we used TCXO 10MHz for CLKIN0 as PLL1 reference input with a PFD of 0.1/ 1MHz.
Thanks
  • 0
    TI__Genius 10985 points

    Hello KLN,

    KLN said:
    Is it okay to feed the PLL1 Reference clock of 100MHz

    If you're wondering whether you can input a 100MHz signal through CLKin1 that then goes to PLL1, then yes, this can be done.

    KLN said:
    Is the PFD of PLL1 will have any issues? Due to high R & N-divider

    From your explanation above, my understanding is that you are feeding in a 100MHz signal to the LMK04832 and then outputting a 100MHz that will be fed in to your 100MHz-VCXO, so there should be no problem in the R/N divider magnitudes, in fact you could divide each by 3 and achieve lock on PLL1. The image below shows an example of said config (ignore PLL2).

    KLN said:
    What value of PFD, Do you suggest for this case? As Fpd1 is 40MHz for PLL1

    Since you have a VCXO that's cleaning your signal, the PFD frequency does not matter as much while it's less than 40MHz. Generally, we recommend for customers to maximize their PFD since a higher PFD/lower N-divider will result in a cleaner signal. But because of the VCXO and its nature of cleaning a signal and you already inputting a signal that's pretty clean (-140dBc/Hz as you mentioned), the PFD frequency doesn't matter much.

    Good Luck,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Intellectual 320 points

    Hi Andrea, 

    Thanks for your response.

    I thought we have to keep the PFD of PLL1 to be lower for better performance. 

    Thanks.

  • +1 in reply to KLN
    TI__Genius 10985 points

    Other way around, higher PFD will result in better performance.

  • 0 in reply to Andrea Vallenilla
    Intellectual 320 points

    Ohh okay. Thanks, Andrea