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# LMX2820: locking a 100 MHz

Part Number: LMX2820

Hello

I would like to lock an external VCO with LMC2820

The problem I have is that the VCO is around 100MHz

I cannot use the RFIN input (pin 28) due to the limit of the minimum frequency requirement for this input.

I want to use instead the PFDIN (pin 20)

I think it should work but I do not know if other designers tried this or not.

I have included a sketch with the connection I like to use.

Thank you!!!

1998_001 (3).pdf

• Hi Aurelian,

You're approach is correct, this is possible.
Please note you cannot use a 100 MHz PFDin but there is a divider where you can reduce it to 20-25MHz or even 50 MHz.

Regards,

Vicente

• Hello Vicente, The way it is in the drawing, the VCO is applied at pin 28-RFIN, this input is specified for a minimum frequency of 1GHz, while the VCO frequency is 100 MHz. But according to the data sheet at PFDin input, pin 20 we can apply frequencies in 20-2000MHz range.

• You can put the 100MHz VCO into the external PFD pins, it's just another N-divider that's integer-only and smaller maximum magnitude. But it gets a little complicated.

• Your input is listed as 10MHz; you could use 5MHz, 10MHz, or 20MHz PFD without issues.
• External PFDIN input has about 3dB worse FOM than the other paths, on account of the need to utilize only a single PFD. Given that your best case N-divider is 5 or 10, and using the formula in footnote 8 of the LMX2820 datasheet electrical characteristics, your PLL flat noise will be either -149dBc/Hz or -152dBc/Hz nominal, though this might improve with reductions in charge pump gain. Unless your reference is exceptional (-170dBc/Hz or better), the reference contribution will dominate in-band noise regardless. For reference, the flicker corner for a 100MHz output at 10kHz is about -156dBc/Hz.
• You would have to operate in single PFD mode, which enables manual PFD delay control - this may take some experimentation to find the best value for 100MHz and your phase detector. Sub-optimal choices for PFD delay can lead to larger PFD spurs.
• It's not clear to me whether we can disable the internal VCO AND the sigma-delta N-divider + RFIN buffer paths at the same time, but there are considerable advantages in both power and spurious performance expected if we can do this. Checking the undisclosed field descriptions internally, I see that we have settings to control each of these paths, but since they are currently undisclosed, it will take some time to investigate exactly how to write them to disable unnecessary paths.

Let me check internally and I'll get back to you about how to handle the unused path powerdown.

• Thank you very much Derek!!!

• Update:

If we configure the device with EXTVCO_EN = 1 and PFD_SEL = 0, even turning off as much of the disclosed functionality as we can, there's potentially 100mA worth of internal functions that can be disabled. Although I've identified the register bits, I'm still waiting on confirmation about whether each register bit corresponding to an unnecessary internal function can be set in a powerdown state without causing long-term issues. If we power down something in an unplanned way, it's possible that there could be unexpected leakage paths between functional blocks within the device, or it may have long-term impacts on reliability. Once (or perhaps if) the device designers confirm that there are no unintended side effects, I'll share the list.

• Thank you very much Derek!!!!!

• Quick follow-up: we determined some additional settings that should be allowable. Note that these are largely in reserved registers, but they represent powerdown operations on unused circuit blocks within the device (VCOs, fractional N-divider, EXTVCO buffer, etc). The rest of the register map reserved bits should be written as suggested.