CDCM9102: [CDCM9102RHBR] Configuration Clock Output Format

James Jang

Prodigy 20 points

Part Number: CDCM9102
Other Parts Discussed in Thread: LMK3H0102

Hi TI Experts,

Could you verify how to configure OS[1:0] Configuration pins to format the PCIe Reference Clock ?

OUT0: LVDS clock output format
OUT1: HCSL clock output format.

It seems that datasheet show either output mode as LVDS or LVPECL.

Datasheet page 15 shows how to terminate LVPECL to HCSL.

If Output formats set to LVPECL, OS1=HIGH, OS0=LOW,

Should terminate OUT0 from LVPECL to LVDS for LVDS Output Format ? If yes, do you have suggested termination method ?

Best Regards,

James

9 months ago

+1 Kadeem Samuel 9 months ago

TI__Genius 17260 points

James,

This can be achieved by setting both outputs to LVPECL (OS1=HIGH, OS0=LOW), then using external termination to convert to LVDS and HCSL:

Alternatively, the LMK3H0102 can natively support LVDS and LP-HCSL (lower power and does not require the external termination resistors required by HCSL).

Thanks,
Kadeem

+1 James Jang 9 months ago in reply to Kadeem Samuel

Prodigy 20 points

Thanks Kadeem, Awesome for your support; could you point me where do you refer to the LVPECL to LVDS Termination shown above ?

+1 Cris Kobierowski 9 months ago in reply to James Jang

TI__Expert 3765 points

Hello,

The image from from this document: https://www.ti.com/lit/an/scaa059c/scaa059c.pdf

Best,

Cris

+1 James Jang 9 months ago in reply to Cris Kobierowski

Prodigy 20 points

Thanks Cris. It is much helped.

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Clock & timing

Clock & timing forum

CDCM9102: [CDCM9102RHBR] Configuration Clock Output Format