Hello,
I am designing a chassis system with fourteen data cards and one clock card. Each data card comprises seven JEDS204b devices. All 14x7 = 98 devices must be synchronized according to JESD204 Subclass 1.
The clock card is equipped with a 3 GHz CLK generator and a controller that triggers a SYNC signal.
My initial concept was to utilize three LMK04832 (building a clock tree) on the clock card to generate fourteen CLK and SYSREF pairs. The first LMK receives the SYNC signal and generates two CLK and SYSREF pairs, which then connect to two LMKs operating in distribution mode (CLKin0 is used to distribute a SYSREF signal through the LMK). The clock card generates fourteen CLK and SYSREF pairs distributed to fourteen data cards. Each data card consists of one LMK operating in distribution mode.
However, a potential vulnerability in this design is the setup/hold of CLK and SYSREF inputs to each LMK operating in distribution mode.
I would like to know if it is possible to determine the location of the SYSREF signals relative to the CLK signals by reading back the amount of setup/hold margin on the interface through the memory map. In the distibution mode, the SYSREF is re-clocked by CLK.
Or maybe you have another idea how to implement it with another IC?
