PLL Lock on the CDCE62005EVM

Hi Kerri,

The LVCMOS input should be connected to PRI_REF+. We have an ac coupled capacitor in the input line by default. Please remove that capacitor (C77) and place a zero ohm resistor for LVCMOS input.

You can improve your PLL settings using attached configuration ( I assume you have 10 MHz clean clock). If you have 10 MHz noisy clock, you may need to use external loop components.

Why are you using some 10 MHz outputs from PLL and other from PLL bypassed.

Thanks,

Firoj

Thanks for your response, Firoj. 

I'm unfortunately still having issues with the unit.  I have 10MHz in on PRI_REF+ and have replaced the C77 capacitor with a 0 ohm resistor; unfortunately I still cannot achieve PLL lock. 

To test the unit, I selected Aux in as my primary input (changed ref in to 25) and used the frequency tool to set loop parameters to get 10MHz out.  with the on board 25MHz crystal and using the settings from the frequency tool, I cannot achieve PLL lock on the unit.  It seems to me that this should work.  Do you have a test I can run to make sure my hardware is working?  Given that I cannot achieve PLL lock with the on board crystal, I believe that the board I have is faulty. 

Thanks,

Kerri

Hi Kerri,

Right after power up and programming the device (I assume you have input clock available), you need to calibrate the PLL.  If you hit the calibrate button in the GUI, it should calibrate the VCO and PLL should be locked. Please see the VCO calibration section in the datasheet (page 67).

If you don't provide any input clock to PRI_REF or SEC_REF, then just power up the EVM/device. The PLL should be locked at default with 25 MHz crystal input. You should see default output frequencies mentioned in the datasheet  (page 23).

Thanks,

Firoj

Hi Firoj,

I'm not convinced that my CDCE62005EVM module is working. 

I disconnected the external 10MHz source from PRI_REF+ and set the device up to use the 25MHz Aux in source and output 10MHz and I cannot get the device to PLL lock.  Here are the steps:

1. disconnect external source

2. connect device to windows machine and open CDCE62005 application

3. put 25 MHz in the aux in line

4. change SmartMux to select aux in

5. use the "Frequency Planner" tool to configure registers for a 25MHz in and a 10MHz out

6. Write EEPROM unlocked

7. Power cycle the device with 'Reset' user button

RESULT: Device Comm light comes on, PLL lock light flashes for < 1s and then goes off. 

Can you please send me register values that enable PLL lock with internal 25MHz source?  Is there any other way to test the hardware to make sure it is working as expected?  I suspect that it is not. 

Thanks,

Kerri

Hi Firoj,

The default settings do not result in PLL lock on the device.  My e-mail is kerrist@lgsinnovations.com.  Can you please e-mail me, and I will call you?  

Thanks,
Kerri 

Thanks for your help today, Firoj! 

I really appreciate it. 

--Kerri