Hello,
I have a customer working with the LMX2595 for a project and we have some questions that we're hoping you can provide guidance on. Please see a summary of the use-case and questions below!
We are using the LMX2595 for signal generation in an FMCW radar. We require repeatable frequency alignment from chirp to chirp (ramp to ramp) relative to ramp trigger edge. We are synchronously driving RampClk pin to trigger the start of each ramp.
Normally we run the Fpd at 100 MHz and drive OSCin with a 100 MHz reference. However, to shift some of the spurs, we sometimes need to run Fpd at 120 MHz or 125 MHz with the same OSCin of 100 MHz. To ensure frequency consistency from chirp to chirp, I plan to synchronize the clock dividers in the FPGA and in the LMX2595 using the SYNC pin. We would then only assert RampClk when the 100 MHz OSCin and the 120/125 MHz Fpd edges align. (Every 5th clock cycle for an Fpd of 120 MHz, and every 4th clock cycle for 125 MHz.)
To be clear, we are not concerned about the output phase of the LMX2595. We care only about the frequency ramp relative to RampClk pin trigger edge. This is a little different than typical usage of the SYNC pin.
Two questions:
- Is RampClk always clocked by OSCin first before being reclocked by Fpd? Or is RampClk clocked in from the pin directly by Fpd?
- In one place in the datasheet it says, "The rising edges are applied to the RampClk pin are reclocked to the phase detector frequency." Then in "6.6 Timing Requirements", it specifies setup/hold times for RampClk relative to OSCin.
- If it is, can we use the SYNC pin to achieve a deterministic delay between OSCin and Fpd clock edges?
Let us know if anything needs further clarification!
-Matt
