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LMX2572LP: PLL simulation

akihiko yokouchi
Intellectual 340 points
Part Number: LMX2572LP
Other Parts Discussed in Thread: , LMX2581, LMX2572

How about an update on PLLatinum Sim.
I am running a simulation with LMX2572LP.
I ran the PLL simulation and saved the results (Fig 1).
Then I load the results and input 280MHz again and the loop bandwidth and phase margin values change (Fig 2).
Which result is correct?
I downloaded the PLLatinum Sim from the website (Fig 3), but the situation remains the same.
I would like to know the correct result as I will start PCB design in the near future.

Regards,
Akihiko Yokouchi

Fig 1

Fig 2

Fig 3

  • 0
    TI__Mastermind 28802 points

    Hi Akihiko-san, 
    In one case you have the simulator try to auto calculate the loop bandwidth and in the second case you have it try to design your filter at 150kHz hence the differences. 
    Is it possible to use a 100 MHz input signal? This way your PFD frequency can be as high as possible for optimal phase noise performance. 

    Regards, 

    Vicente 

  • 0
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    Right, I have the same issue, I will inform the developer to fix this problem. I believe 57.6MHz/V is the correct Kvco at that VCO frequency.

  • 0 in reply to Noel Fung
    Intellectual 340 points

    Hi Vicente,Noel,

    Thanks for the confirmation.

    We will consider the loop filter (characteristics) with the modulation sensitivity (Kvco) set to 57.6 MHz/V.
    It is difficult to set Fosc to 100MHz.
    I would like to increase the Fpd to improve the phase noise, but it will be 10MHz.

    I have purchased the LMX2572LPEVM.
    It will be in my hands soon.

    As previously reported, with LMX2581, spurious due to Fpd:10MHz occurred near Fout:280MHz.
    I have heard that LMX2572LP does not generate spurious near Fout:280MHz as LMX2581 does, is this correct?

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Mastermind 28802 points

    Hi Akikho, 
    You can use the doubler to have a Fpd of 20 MHz for some improvement. 
    I would expect crosstalk spurs at every 20kHz offsets from carrier 

    Regards, 

    Vicente 

  • 0
    TI__Mastermind 27981 points

    Hi,


    The difference is due the the different VCO gain.  You can change the VCO gain to see this

    Based on the datasheet on the web, page 59, VCO gain is 47 at 4200 MHz and 64 at 4650

    So 47 + (4480 - 4200)*(64-47)/(4650-4200) 57.6 MHz/V, so figure 1 seems correct.

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    Right, LMX2572 does not have the spurs issue as LMX2581.

    Here is the test data, I do see a small spurs at 120MHz, which is due to OSCin.

  • 0 in reply to Noel Fung
    Intellectual 340 points

    Thank you all for contacting me.

    Hi Vicente

    Regarding crosstalk spurious at 20 kHz offset from the carrier.
    Would this occur at Fosc:10MHz and Fpd:20MHz (Input Multiplier:2)?
    The spurious spacing will be wider than at Fpd:10MHz, but this is not convenient if the spurious level is high like in LMX2581.

    Hi Dean

    Thanks for the modulation sensitivity (Kvco) calculation.

    Hi Noel

    Thank you for the actual measurement.
    At the time of this measurement, I think Fosc:160MHz and Fpd:160MHz.
    A spurious level of Δ160MHz should not be a problem.

    Higher Fpd is better for phase noise, but Fosc is 10MHz (I don't plan to go higher than 10MHz for now).
    I think we can increase the Fpd with Input Multiplier, but I am concerned about the spurious level generated before and after the multiplier.
    I am going to check these concerns on the evaluation board.

    Please let me check again (although I think it would be better to check with the evaluation board).
    Is it safe to assume that the LMX2572LP has a lower (less noticeable) spurious level at 10MHz intervals around 280MHz than the LMX2581 when Fosc:10MHz and Fpd:10MHz are set?
    If it is the same as the LMX2581, I would like to start a circuit study to set Fosc to about 120MHz.

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    My plot is with 10MHz fpd and fosc, the 120MHz spurs is due to the 10MHz OSCin.

  • +1 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Understood.
    As soon as I get the evaluation board, I will check things out.
    Thank you very much for your confirmation and other responses.

  • 0 in reply to akihiko yokouchi
    Intellectual 340 points

    Hi Dean,

    I would like to confirm something about LMX2572LP (PLLatinum Sim).

    When fout:280MHz, the modulation sensitivity is 57.6MHz.
    At this time, VCO3 is selected as the VCO, and the modulation sensitivity (Kvco) matches the calculated value (Fig. 1).

    We can see that VCO2 is selected at fout:455MHz.
    At this time, Kvco is 35.3 MHz/V, which does not match the value calculated from Table 134.
    And from Table 134, the fmin of VCO2 is 3650 MHz, but is it safe to use it for Fvco:3640 MHz (Fig. 2)?

    Furthermore, assuming Table 134 is correct.
    If VCO is selected as VCO1, VCO1 can be confirmed to be 3200-3600MHz and does not match Table 134.
    It also does not match the calculated value of Kvco (even if fmax:3600MHz) (Fig. 3).

    Which VCO should be used for Fout:455MHz?
    Also, is Table 134 correct for the oscillation frequency of the VCO?
    Or is PLLatinum Sim correct?

    Regards,
    Akihiko Yokouchi

    fig1

    fig2

    fig3

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    Dean will fix the mismatch between datasheet and PLL sim.

    Please note, in reality, adjacent VCO core have overlapping frequency region. For example, VCO1 and VCO2. around 3650MHz, both VCO cores can support. When we do a no-assist VCO calibration, the algorithm will pick the best VCO core to use. It could be VCO1, it could also be VCO2. The decision will depend on the environment (e.g. temperature) and part-to-part variation. 

    Since Kvco change with frequency, you can use the mean Kvco value in your loop filter design. For example, if you need VCO1, 2 and 3. Kvco will vary between 32 to 64MHz/V. Mean value is sqrt(lowest Kvco * highest Kvco). 

  • 0 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Thank you for contacting us.

    Will you be modifying the table in the catalog?
    Or would you modify the PLLatinum Sim?

    Is it safe to continue to consider the loop filter?
    If we modify the PLLatinum Sim, would it be better to download the latest version and then consider it?

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    We will update PLL Sim to match datasheet.

    It is absolutely safe to continue using the current version PLL Sim. As I explained before, after VCO calibration, it may use VCO1 or VCO2. You can do your design with either VCO or use the mean Kvco to design.

  • +1 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Understood.
    We will proceed with the loop filter study.
    Thank you for your response.

  • 0 in reply to akihiko yokouchi
    Intellectual 340 points

    Hi Noel,

    The characteristics were verified with the LMX2572LP evaluation board.
    As a result, it was confirmed that the phase noise was almost the same as that of the simulation.
    We also confirmed good results for spurious.
    Thank you very much for your support.

    Regarding the LMX2572LP(TICS Pro) settings.
    I don't think there are any problematic settings, but please advise me if there are any settings that you think would be better.

    Regards,
    Akihiko Yokouchi

    (1)Fosc: 10MHz, Fpd: 10MHz, RFout: 280MHz.
    (2)Fosc: 10MHz, Fpd: 10MHz, RFout: 455MHz.

    IC setting for (1)

    R125 0x7D0820
    R124 0x7C0000
    R123 0x7B0000
    R122 0x7A0000
    R121 0x790000
    R120 0x780000
    R119 0x770000
    R118 0x760000
    R117 0x750000
    R116 0x740000
    R115 0x730000
    R114 0x727802
    R113 0x710000
    R112 0x700000
    R111 0x6F0000
    R110 0x6E0000
    R109 0x6D0000
    R108 0x6C0000
    R107 0x6B0000
    R106 0x6A0007
    R105 0x694440
    R104 0x682710
    R103 0x670000
    R102 0x660000
    R101 0x650000
    R100 0x642710
    R99 0x630000
    R98 0x620000
    R97 0x610000
    R96 0x600000
    R95 0x5F0000
    R94 0x5E0000
    R93 0x5D0000
    R92 0x5C0000
    R91 0x5B0000
    R90 0x5A0000
    R89 0x590000
    R88 0x580000
    R87 0x570000
    R86 0x560000
    R85 0x55D800
    R84 0x540001
    R83 0x530000
    R82 0x522800
    R81 0x510000
    R80 0x50CCCC
    R79 0x4F004C
    R78 0x4E0001
    R77 0x4D0000
    R76 0x4C000C
    R75 0x4B0940
    R74 0x4A0000
    R73 0x49003F
    R72 0x480001
    R71 0x470081
    R70 0x46C350
    R69 0x450000
    R68 0x4403E8
    R67 0x430000
    R66 0x4201F4
    R65 0x410000
    R64 0x401388
    R63 0x3F0000
    R62 0x3E00AF
    R61 0x3D00A8
    R60 0x3C03E8
    R59 0x3B0001
    R58 0x3A9001
    R57 0x390020
    R56 0x380000
    R55 0x370000
    R54 0x360000
    R53 0x350000
    R52 0x340421
    R51 0x330080
    R50 0x320080
    R49 0x314180
    R48 0x3003E0
    R47 0x2F0300
    R46 0x2E07F0
    R45 0x2DC608
    R44 0x2C07A3
    R43 0x2B0000
    R42 0x2A0000
    R41 0x290000
    R40 0x280000
    R39 0x270001
    R38 0x260000
    R37 0x250205
    R36 0x2401C0
    R35 0x230004
    R34 0x220010
    R33 0x211E01
    R32 0x2005BF
    R31 0x1FC3E6
    R30 0x1E0CA6
    R29 0x1D0000
    R28 0x1C0488
    R27 0x1B0002
    R26 0x1A0808
    R25 0x190624
    R24 0x18071A
    R23 0x17007C
    R22 0x160001
    R21 0x150409
    R20 0x144848
    R19 0x1327B7
    R18 0x120064
    R17 0x110096
    R16 0x100080
    R15 0x0F060E
    R14 0x0E1878
    R13 0x0D4000
    R12 0x0C5001
    R11 0x0BB018
    R10 0x0A10F8
    R9 0x090004
    R8 0x082000
    R7 0x0700B2
    R6 0x06C802
    R5 0x0530C8
    R4 0x040A43
    R3 0x030782
    R2 0x020500
    R1 0x010808
    R0 0x00201C

    IC setting for (2)

    R125 0x7D0820
    R124 0x7C0000
    R123 0x7B0000
    R122 0x7A0000
    R121 0x790000
    R120 0x780000
    R119 0x770000
    R118 0x760000
    R117 0x750000
    R116 0x740000
    R115 0x730000
    R114 0x727802
    R113 0x710000
    R112 0x700000
    R111 0x6F0000
    R110 0x6E0000
    R109 0x6D0000
    R108 0x6C0000
    R107 0x6B0000
    R106 0x6A0007
    R105 0x694440
    R104 0x682710
    R103 0x670000
    R102 0x660000
    R101 0x650000
    R100 0x642710
    R99 0x630000
    R98 0x620000
    R97 0x610000
    R96 0x600000
    R95 0x5F0000
    R94 0x5E0000
    R93 0x5D0000
    R92 0x5C0000
    R91 0x5B0000
    R90 0x5A0000
    R89 0x590000
    R88 0x580000
    R87 0x570000
    R86 0x560000
    R85 0x55D800
    R84 0x540001
    R83 0x530000
    R82 0x522800
    R81 0x510000
    R80 0x50CCCC
    R79 0x4F004C
    R78 0x4E0001
    R77 0x4D0000
    R76 0x4C000C
    R75 0x4B08C0
    R74 0x4A0000
    R73 0x49003F
    R72 0x480001
    R71 0x470081
    R70 0x46C350
    R69 0x450000
    R68 0x4403E8
    R67 0x430000
    R66 0x4201F4
    R65 0x410000
    R64 0x401388
    R63 0x3F0000
    R62 0x3E00AF
    R61 0x3D00A8
    R60 0x3C03E8
    R59 0x3B0001
    R58 0x3A9001
    R57 0x390020
    R56 0x380000
    R55 0x370000
    R54 0x360000
    R53 0x350000
    R52 0x340421
    R51 0x330080
    R50 0x320080
    R49 0x314180
    R48 0x3003E0
    R47 0x2F0300
    R46 0x2E07F0
    R45 0x2DC608
    R44 0x2C07A3
    R43 0x2B0000
    R42 0x2A0000
    R41 0x290000
    R40 0x280000
    R39 0x270001
    R38 0x260000
    R37 0x250205
    R36 0x24016C
    R35 0x230004
    R34 0x220010
    R33 0x211E01
    R32 0x2005BF
    R31 0x1FC3E6
    R30 0x1E0CA6
    R29 0x1D0000
    R28 0x1C0488
    R27 0x1B0002
    R26 0x1A0808
    R25 0x190624
    R24 0x18071A
    R23 0x17007C
    R22 0x160001
    R21 0x150409
    R20 0x144848
    R19 0x1327B7
    R18 0x120064
    R17 0x110096
    R16 0x100080
    R15 0x0F060E
    R14 0x0E1878
    R13 0x0D4000
    R12 0x0C5001
    R11 0x0BB018
    R10 0x0A10F8
    R9 0x090004
    R8 0x082000
    R7 0x0700B2
    R6 0x06C802
    R5 0x0530C8
    R4 0x040A43
    R3 0x030782
    R2 0x020500
    R1 0x010808
    R0 0x00201C

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    The configurations look fine.

  • +1 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Thanks for the confirmation.

  • 0 in reply to akihiko yokouchi
    Intellectual 340 points

    Hi Noel,

    I would like to confirm about OSCin of LMX2572LP.
    When the OSCin TYPE is SINGLE-ENDED CLOCK, is it OK to input to either OSCINP or OSCINM?
    Or is there a recommended input (OSCINP? or OSCINM?)?

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    Single-ended buffer uses OSCINP as its input.

  • +1 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Understood.
    Thanks for the confirmation.

  • 0 in reply to akihiko yokouchi
    Intellectual 340 points

    Hi Noel,

    　Please allow me to confirm regarding the MLX2572LP function.

    　Is it possible to slow down the response to Fosc fluctuations by changing some setting in the LMX2572LP?

    　There are Fosc1 (10MHz) and Fosc2 (10MHz), both are 10MHz but the frequency is slightly different.
    　When switching from Fosc1 to Fosc2, Fout would normally fluctuate at a certain speed.
    　I would like to make this fluctuation change slowly, not abruptly.

    　Is the only way to do this is to use a loop filter to make it fluctuate slowly, rather than some setting in the LMX2572LP?
    　
    　If the loop filter is the only way to handle this.
    　Is it possible to consider this in the PLLatinum Sim?
    　Is setting the Lock Time intentionally long enough to slow down the response?
    　Any advice on how to slow down the reaction would be appreciated.

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    Hi Yokouchi-san,

    When switching from Fosc1 to Fosc2, obviously it would be a break-before-make kind of switch over. Therefore, there will a certain time interval without a reference clock to the PLL. In this period, the PLL will unlock. If this period is less than a fpd period, we may not notice any fluctuation at the output.

    To reduce the sensitivity to fosc change, we can use a narrow bandwidth loop filter with high charge pump current. This way, some of the loop filter capacitors value will be big. We want to use these big capacitors to maintain Vtune voltage during the break period. 

  • 0 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    　Thanks for the advice.
    　I will consider it.

    　Please let me check with PLLatinum Sim.
    　In the explanation of Frequency Response of Lock Time, does "PLL Lock Time" mean "Analog Lock Time" ?(Fig 1)

    Regards,
    Akihiko Yokouchi

  • 0 in reply to akihiko yokouchi
    TI__Guru** 106720 points

    That's is correct.

  • +1 in reply to Noel Fung
    Intellectual 340 points

    Hi Noel,

    Thanks for the confirmation.