Part Number: LMK04806
Hi Ti expert,
My customer is using LMK04806 to output many kinds of clocks to other DACs and FPGAs. Input clock is 100MHz.
Customer finds that there is a 1.2G phase noise as below, which can be solved by replace a new LMK04806. Customer suspected that it was a problem with the IC itself.
Could you please help check the schematic and layout.
Hi William,
Could you check the register config of LMk04806 through picture.
Gary,
TICSPro is the software used to program many clocking devices. You can download it here.
Once you configure the settings you can share them easily by pressing File->Save. This will create a .tcs file which contains your register values.
Regards,
Will
Gary,
Testing on the EVM I was able to find what was causing the PLL not to lock.
I noticed that PLL2_N_CAL was set to 12, when it should match PLL_N which you set to 10 in the PLL2 GUI page.
When writing only PLL2_N_CAL to 12, lock was not lost. But when writing PLL2_N_CAL to 12 and then rewriting all other registers, lock was lost because the VCO was triggered to recalibrate and PLL2_N_CAL and PLL2_N are not the same value as they should be.
Let me know if you need any more help.
Regards,
Will
