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LMK05318B: Clock frequency combination possibility and 10MHz generation query

Navadeep Ganesh U
Prodigy 20 points
Part Number: LMK05318B
Other Parts Discussed in Thread: LMK5B33216

Hello TI team, 

I am trying to evaluate LMK05318B for one our designs and following is the requirement:

IN: 40MHz XTAL, 40MHz recovered clock

OUT: 156.25MHz(HCSL), 122.88MHz(LVCMOS), 40MHz(HCSL) and 10MHz(LVCMOS)

Is this combination possible with single chip LMK05318B?

Trying out in your webench clock tree architect tool, as expected the chip is generating two arbitrary frequencies required using APLL1 and 2. Alongside, 10MHz is also given which is shown is from VCO1. For 40MHz, the tool is recommending to go with another chip cascaded to it's 10MHz output. So my query is:

  1. How is the chip able to get 10MHz alongside the 156.25MHz while it is not an integer divided value from 156.25MHz? (it is only 10MHz and not any other frequency seen possible)
  2. One of the datasheet example cases (page 76) show the generation of 100MHz and 25MHz along with two aribitary frequencies. From what configuration are these numbers arrived?

  • +1
    TI__Genius 13630 points

    Hi Navadeep, 

    It won't be possible to generate 156.25 MHz, 40 MHz, 10 Mhz, and 122.88 MHz outputs at the same time with LMK05318B. Like the clock tree architect tool shows, 156.25 MHz and 10 MHz can both be derived from APLL1, since 2500 MHz is an integer multiple of both frequencies. 40 Mhz and 122.88 MHz don't have an integer relationship with 2500 MHz so they would need to be derived from APLL2. However, no common multiple of these frequencies falls within APLL2's allowable VCO range of 5.5 GHz to 6.25 GHz. 

    Do you need DPLL functionality, or do you just a clock generator? If a DPLL is still needed, you could use LMK5B33216 since it has 3 APLL/DPLL pairs and can generate 3 different frequency domains.

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    Prodigy 20 points

    Helpful. Thanks for the part suggestion as well.