LMK04828: Generating a phase-aligned 10MHz output clock

Matt,

I will get back to you by Thursday.

Regards,

Will

Hello Matt,

Could you attach the .tcs file? I don't believe I am seeing your correct config. I included a screenshot below of the register dump you included and what I'm seeing on my end.

Matt Fransham said:

With this configuration, should I expect the CLKin0 input and the SDCLKout11 output to be both frequency and phase aligned?

To ensure frequency and phase alignment, apart from configuring the part correctly, you need to follow a set of steps to correctly synchronize all of your outputs. I have included it below and it's also (worded differently) in p. 40.

Steps to achieve synchronization:

1. Need to enable SYNC circuitry to synchronize the output dividers.
   • SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0, SYSREF_PD = 0, SYNC_EN = 1.
2. Clear local SYSREF DDLY.
   • SYSREF_CLR = 1 (forgot to mention this in the call).
3. Enable dividers to be accepted by SYNC pulse to synchronize.
   • SYNC_DISX = 0 for all outputs needed to be synced (i.e if outputs 3 and 8 need to be synced, then set SYNC_DIS2 = 0 and SYNC_DIS8 = 0).
4. Toggle SYNC_POL to generate sync pulse that triggers output dividers to be synced.
   • SYNC_POL = 1, SYNC_POL = 0.
5. Disable another rising edge that comes from SYSREF to reset the output dividers.
   • SYNC_DISX = 1 (i.e from previous example, set SYNC_DIS2 = 1 and SYNC_DIS8 = 1).
6. Release reset of local SYSREF digital delay.
   • SYSREF_CLR = 0.
7. Set SYSREF to desired operation.
   • SYSREF_MUX = 1, 2, or 3 (2 = SYSREF pulser and 3 = SYSREF continuous).

Matt Fransham said:

If I configure LMK chips similarly on different boards and provide them an equivalent 10MHz reference can I expect the SDCLKout11 outputs on all boards to be aligned?

The same steps mentioned above need to be performed in all the chips and the SYNC pin needs to be used to achieve alignment. Basically, all boards need a common clock to base their phase alignment upon, and you would have one clock generate this clock, called SYSREF, to all the other clocks/chips. So you would have an output of on LMK04828 feed into the SYNC/CLKin0 pins of the other LMK boards. The original LMK04828 board would generate SYSREF pulser and send that pulse to the boards to trigger the peripheral boards to SYNC on the high edge of that pulse.

This article will comment more about doing this and having multi-board synchronization. Would recommend looking at sections 2 and 3 or Section 4 for ZDM and Figure 11 + the text below it. This is also a good reference on synchronizing multiple chips on a similar part, the LMK04610. If possible, read both articles fully.

Matt Fransham said:

Do I need to somehow trigger a SYNC event in order to get phase alignment to occur?  I saw mention of this in a different post.

Correct, more information on explanation and articles above.

Hi Andrea,

Thanks for the reply.  I still need to read through it in detail but wanted to provide the TICS file.  The issue may be the input frequencies - I am not sure those get reflected in the register file.  The inputs frequencies should be 10MHz for CLKin0, 10MHz for CLKin1 and 160MHz for the oscillator.

Matt

CustomHexValues_ClkIn0_zerodelay.tcs

Hello Matt,

Is the 10MHz the clock you're sharing across your devices, correct? That 10MHz is not clocking anything else?

Also, to clarify, your config has several outputs at different frequencies (10MHz, 125MHz, and 250MHz), is that what you want? From your description above it seems you wanted just 10MHz being fed through your system.

Best,

Andrea

Hi again.  I've read through your response and wanted to provide a bit of a higher-level system context before asking some follow-up questions.  As shown in the diagram below, multiple boards are connected through a High-Precision Timing Distribution Network and we don't have the ability to distribute signals directly from one board to another:

Some additional notes about the design:

• 1PPS and 10MHz signals are distributed to multiple boards through a High Precision Timing Distribution Network.
• Assume very little offset/jitter between 10MHz references to the different boards.
• Sync'd 1PPS signal is also distributed with this clock.
• Inside each FPGA there is a Time of Day Counter.  These can in theory be closely synchronized between boards using the distributed 1PPS and 10MHz signals.
• In the diagram, the 10MHz is shown going through the LMK to the FPGA and then the "regenerated" SDCLKoutY clock is used on each board to clock the Time of Day Counter.  The idea is to use the 10MHz to ensure that the TOD counter increments at the right frequency, and then the 1PPS is used to align "phase" of the TOD counter across multiple boards.
• With locked Time of Day counters, the idea is that different boards can be instructed to generate SYNC signals at a precise moment in time.  This would result in "synchronized" SYNC signals being generated on all boards to synchronize all dividers and ensure all "other" clocks for ADC/DACs are locked across boards.  So, the SYNC signal will in theory be sync'd across boards because they all have locked TOD, but at the same time it would be generated independently by each board and not a common signal distributed to all boards.

I am running into a few concerns about whether this will work, though:

• In order to generate an output 10MHz to the FPGAs, it seemed like the only way to do so is using the SYSREF distribution network and an SDCLKout output.  I wasn't able to generate a clock with a 10MHz frequency on any of the DCLKout outputs (the DCLK clock dividers don't provide a large enough option for dividing down the VCO frequency to 10MHz).
• To use the SYNC input, though, the steps involve temporarily reconfiguring the SYSREF distribution network to use the SYNC Pin to reset clock dividers.  
• I think that when I do this, though, I would lose my 10MHz to the FPGA (when I change the value of the SYSREF_MUX), which means I would not longer have the ability to generate the SYNC signal in the FPGA.
• I am wondering whether I can't use an LMK generated clock to generate the SYNC.

Some more specific questions:

• For generating the SDClkOut (10MHz) to the FPGAs, because I'm using zero-delay mode (with SYSREF feedback) and the output clock is the same frequency as the input clock, it seems I shouldn't need the SYNC signal to have these aligned across multiple boards.  Seems like the zero-delay mode handles phase alignment and that there isn't ambiguity about different phase alignments since the frequencies are the same.  Can you confirm?
• Is it true that as soon as I reconfigure the chip to use the SYNC Pin to drive the SYSREF network that I will lose the 10MHz output to the FPGA?  If so, then it won't work to use this clock to generate a SYNC signal across multiple boards.

Summary:

• The high-level idea is that 1PPS and 10MHz get distributed to all boards and are used to synchronize a time-of-day counter.  The 10MHz is used as an input reference to the LMK.  All boards are instructed to generate a SYNC signal at a precise moment in time to synchronize LMK clocks across multiple devices.  But....I'm not sure the current scheme of passing the 10MHz used for TOD generation through the LMK is possible.  Maybe the 10MHz needs to go straight to the FPGA somehow.

Hello Matt,

I'll get back to you by the end of next week.

Best,

Andrea

Hello Matt,

I've read your response at a higher level, to clarify and before continuing to discuss the 4828, do you need the LMK04828 to handle a 1pps signal?

Best,

Andrea

Hi Andrea,

The inputs I have to each endpoint are only a synchronized 10MHz and 1PPS signal from the timing distribution network (no ability to send signals between the different endpoints directly).  I want to generate locked 10MHz, 125MHz and 250MHz clocks between all endpoints.  It isn't clear to me that the 1PPS needs to go to the 4828, but at the same time, it seems to me that cross-board synchronization will require generating synchronized SYNC signals across all boards.  The 1PPS seems necessary for doing this somehow.  I think I can get sync'd 10MHz and 250MHz signals across each board without a common SYNC signal since the frequencies are all nice multiples.  But the 125MHz would require extra inter-board synchronization since it isn't a nice multiple of the 10MHz input and could end up with different phase alignments across different boards.

Does that help clarify?

Matt

Hello Matt,

I'm talking to a colleague that knows more about handling 1pps signal so I can further assist you.

Best,

Andrea

Hi Andrea,

Thank you for the reply.  Switching to the LMK04832 isn't really an option for us since we are using 3rd party development kits.  The info you provided is useful though.

With this extra knowledge, I believe I've been able to remove some of the requirements that are making this difficult with the LMK04828 and come up with a solution that could work for us.

First of all, I can get rid of the 125MHz, so can just deal with 250Mhz and 10MHz.  The 10MHz will be generated with the SYSREF DIVIDER and used for 0-delay mode feedback.  I believe that using the SYNC PIN in SPI mode (i.e. toggle SYNC_POL to reset dividers) should allow me to align the phase of a 250MHz output and the phase of the 10MHz SYSREF DIVIDER to a 10MHz input reference.  This should be deterministic since 250MHz is a multiple 10MHz (no ambiguity in terms of different possible alignments).

If I provide the same 10MHz to a different board and follow the same SPI SYNC method I can also generate 250MHz and 10MHz clocks on that board that are aligned deterministically to the 10MHz reference. Since the 10MHz reference signals are aligned to the different boards, it can be expected that their generated 250MHz and 10MHz outputs will also be aligned (even if the SPI SYNC sequence is performed at a different time).

All this said, the main thing is that I believe I can generate aligned output clocks (10MHz and 250MHz) using the LMK04828 across multiple boards, without actually needing to generate aligned SYNC signals to the input pin of the different devices.  Since all boards get the same 10MHz reference, and the output clocks (10MHz and 250MHz) are nice multiples of this, then SPI SYNC method run on each board should be enough to ensure all clocks are aligned to the reference.

I'm hoping this all sounds correct to you, but if not could you comment on what doesn't seem accurate or possible?

Thanks,
Matt

Hello Matt,

Matt Fransham said:

All this said, the main thing is that I believe I can generate aligned output clocks (10MHz and 250MHz) using the LMK04828 across multiple boards, without actually needing to generate aligned SYNC signals to the input pin of the different devices.  Since all boards get the same 10MHz reference, and the output clocks (10MHz and 250MHz) are nice multiples of this, then SPI SYNC method run on each board should be enough to ensure all clocks are aligned to the reference.

I'm double checking this part with a coworker as I believe there may be an edge case that may not make this true. However, most of the time I believe it should be correct. I will get back to you with a definite answer.

Outside of that, everything else you said it correct.

Best,

Andrea

Hi Andrea,

Thanks for this and apologies for taking a while to respond!

This helps a lot, but one more question.

You say that the SYNC signals must be sent from the same device.  In our case, we are going to need to generate them on separate devices indepndently, put hope to be able to do it in a very synchronized way.

My thinking is to use the Pulser Pin mode, so when the SYNC signal is asserted, the SYSREF will be driven for a programmable number of pulses.  I understand that this mode really just "ungates" the already running 10MHz SYSREF signals (which, as per our discussion above, should all be synchronized across the different boards).

My assumption is that the LMK chip is looking for an edge of the SYNC signal and when it detects that, it will ungate the SYSREF signal at its next edge.  In that case, there might be a little bit of wiggle room when the SYNC signal could be generated in order to get the same results across multiple boards.  For example, if all boards drive the SYNC within the same 10MHz clock period window, then all board will see their SYSREF signal ungated on the same next edge.

Maybe put a bit differently, it seems like even if the SYNC signals aren't driven at exactly the same time across all boards, if they fall within the same 10MHz SYSREF period, all boards could still see their pulsed SYSREF perfectly synchronized.

Does that sound accurate?  

Matt