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LMK04832: Phase-aligned Outputs from Multiple LMK04832s

IDK
Prodigy 230 points
Part Number: LMK04832


Hi,

Could you please sanity check my intended implementation to produce frequency-aligned and phase-aligned clock and SYSREF outputs from multiple LMK04832s? Based on some research, I believe this should result in something at least frequency aligned, but am unsure as to the accuracy of the phase-alignment:

  • All LMK04832s are operating in PLL2 Single Loop Mode with an external loop filter
  • All LMK04832s operate in cascaded 0-delay mode and the feedback MUX is set to the internal SYSREF generated by the VCO
  • All LMK04832s receive a phase-matched 50MHz clock input to OSCIN, which feeds PLL2
  • All LMK04832s receive a phase-matched SYNC input signal that triggers a number of SYSREF pulses 

In 0-delay mode, is the phase relationship from input clock to output clock deterministic between LMK04832s? Will the outputs from both LMK04832s be perfectly phase-aligned or is there some tolerance?

Some block diagrams and images from TICS as a visual:

Thanks,

Matthew

  • 0
    TI__Genius 10995 points

    Hello Matthew,

    I'll get back to you by the end of the week.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    TI__Genius 10995 points

    Hello Matthew,

    IDK said:
    All LMK04832s are operating in PLL2 Single Loop Mode with an external loop filter

    Why are you using an external loop filter if you are using PLL2? Did you corroborate that loop filter gives you a good phase margin using the PLLatinum Sim tool? This is a good E2E to follow to ensure that you are obtaining your desired phase margin.

    IDK said:
    In 0-delay mode, is the phase relationship from input clock to output clock deterministic between LMK04832s? Will the outputs from both LMK04832s be perfectly phase-aligned or is there some tolerance?

    It is phase deterministic from input to output but they may be some tolerance. I'm currently working on determining if there is and if so by how much for another customer case, so I don't have that data available.

    Note this when using SYSREF Pulser (p. 30 on data sheet):

    ...and this in case you are turning on/off a stream of SYSREF pulses externally.

    Finally, I would turn off all delays (SYSREF_DDLY is on in one of your pictures) and achieve output synchronization first. Then I would turn digital delay on and correct any output required to align the outputs of the LMK04832. To synchronize the outputs (this is done after initial configuration is done), follow these steps:

    1. Need to enable SYNC circuitry to synchronize the output dividers.
      • SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0, SYSREF_PD = 0, SYNC_EN = 1.
    2. Clear local SYSREF DDLY.
      • SYSREF_CLR = 1 (forgot to mention this in the call).
    3. Enable dividers to be accepted by SYNC pulse to synchronize.
      • SYNC_DISX = 0 for all outputs needed to be synced (i.e if outputs 3 and 8 need to be synced, then set SYNC_DIS2 = 0 and SYNC_DIS8 = 0).
    4. Toggle SYNC_POL to generate sync pulse that triggers output dividers to be synced.
      • SYNC_POL = 1, SYNC_POL = 0.
    5. Disable another rising edge that comes from SYSREF to reset the output dividers.
      • SYNC_DISX = 1 (i.e from previous example, set SYNC_DIS2 = 1 and SYNC_DIS8 = 1).
    6. Release reset of local SYSREF digital delay.
      • SYSREF_CLR = 0.
    7. Set SYSREF to desired operation.
      • SYSREF_MUX = 1, 2, or 3 (2 = SYSREF pulser and 3 = SYSREF continuous).

    Hope this helps!

    Good Luck,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 230 points

    Hi Andrea,

    Yes we did check that the external loop filter gives us good phase margin using the tool.

    Overall, thanks for the detailed response - I look forward to your findings on if and what the tolerance for the deterministic phase latency may be. Do you have a rough ETA on when that would be available (couple of days to weeks)?

    Thanks,

    Matthew

  • 0 in reply to IDK
    TI__Genius 10995 points

    Hello Matthew,

    Probably around weeks as I need to collect more data in different conditions with different parts. I can get back to you once I collect all info.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 230 points

    Hey Andrea,

    Understood, thanks for investigating this.

    Thanks,
    Matthew