When using the LMK00304 chip to output three 100MHz differential clocks, after measurement, the duty cycle of all output clocks has reached 60%. What is the reason for this? Is there any way to adjust the duty cycle to 50%?
The following three figures correspond to the three output clocks.
Hello,
The duty cycle problem may be caused by an incorrect input bias voltage, because the customer is DC coupling and should be AC coupling. As stated in section 9.1 of the datasheet.
Please tell the customer to change the configuration to the one shown in the datasheet. Also, for better performance it is recommended to use CLKin for single ended inputs instead of OSCin. Please see the datasheet section 9.1 for for the CLKIn single-ended example.
Regards,
Will
Firstly, we removed the 33 Ω resistor numbered R708 and replaced it with two 0.1uf capacitors. The measured duty cycle of the output clock was 46%. Then, we soldered a 50 Ω resistor at position R721 and measured the duty cycle of the output clock to be 68%.
2、Why did the duty cycle fail to reach 50% in the first measurement? Why does the duty cycle increase to 68% after adding a 50 Ω resistor？
Hello,
After doing some work in the lab I have some ideas.
In regards to your first question about why the first measurement failed to reach 50% duty cycle, this is because the input signal was violating the absolute maximum for the input signal. The OSCin pin has an internal bias of ~ .9V so when a 3.3V signal is applied, the negative swing is violating the absolute Min for Input Voltage. .9 - 3.3/2 = -.75. -.75 < -.3
In regards to why your second measurement why adding the 50 ohm to ground further degraded the duty cycle, this is because your design the AC coupling cap is behind the 50 ohm, while in the datasheet recommendation shown above, there are AC coupling caps in behind and in front of the 50 ohm to ground. The reason why a cap is needed between the 50 ohm to ground and the input is because the OSCin pin is weakly biased, so the 50 ohm to ground will pull the bias to 0.
To resolve your problem please follow the design as shown in the datasheet image above. With the 50 ohm you are limiting input overdrive/underdrive and with the cap you are preventing the bias from being pulled down.
I hope this helps. Let me know if you have any further questions.
Regards,
Will
Based on the initial design, we replace R708 with a resistor of 50Ω and R721 with a resistor of 100Ω, so that the VCMD changes from 1.65V to 0.9V. The final measurement results show that the duty cycle of the output clock is 49%. Does this prove that the form of DC coupling can also be used when using OSCIN as the pin for clock input, and there is some flaw in such a design?
