LMK05318B: LMK05318B - Output frequency error - when using 1pps

Email set 24/04/2024: 

Hi Jennifer,

1. Can you please make an e2e post and try uploading the video & files there? Let me know if you still have issues and I can find an alternative method [PH: Will do]
2. Are you using the EEPROM?  [PH: Yes do]
3. Which steps do you follow?
   1. Option A [PH: Operates as per description]

1. Program EEPROM
2. Toggle PDN/power reset board with no 1PPS present

• Still no 1PPS present à OK

1. Apply 1-PPS à not OK
2. Remove 1-PPS à OK
3. Apply 1-PPS à OK

1. 1. Option B [PH: Operates as per description]

1. Load .tcs file
2. Issue a software reset (R12[7]) with no 1PPS present

• Still no 1PPS present à OK

1. Apply 1-PPS à not OK
2. Remove 1-PPS à OK
3. Apply 1-PPS à OK

1. 1. Other ?
2. How do you define “wrong frequency” for the 10MHz output? Is it by measuring on the frequency counter? Checking the input to output phase relationship? [PH: We using a spectrum analyser - 10MHz drops to 9.994MHz – we are not looking at phase, this is not a requirement]

A bit more information from today:-

Looking at register R123:-

0xA8 = Good (Nice 10MHz prior to 1pps)

0x88 = Bad (Not nice 10MHz once 1pps applied)

0xA8 = Good (Once 1pps is removed)

One thing that we are pondering, how is the tuning word history provided for that first instance when 1pps is applied, LOFL is good and IC is out of Holdover?>

Thank you, Paul for uploading this from the email to e2e. We will review.

Regards,

Jennifer

Hi,  

Very important find by Simon:--

He debugged register by register and arrive at a config that passed (no 10M jump)

Working with :R260 register  Bit4 appears to affect the operation '0' Fail - '1' - Pass

We still need to prove the chip is in lock - even though LOFL is low.

What is R260 Bit4 doing? 

Some further questions:-- 

What does R267[7:4] do? Its set to 0b1010 but datasheet says reserved, leave as 0b0000. Causes APLL1 to jump around every 1S when disciplining to 1PPS.

R222 is called REF0_HOLD_CNTSTRT_BY2 in the register list, but contains PRIREF_FREQ_DET_10.

Files attached for FAIL: PLC_LMK_V3 WIP

FAIL: PLC_LMK_V3 WIP - with potential fix

Thankyou 

5277.PLC_LMK_V3 WIP.tcsPLC_LMK_V3 WIP - with potential fix.tcs

Hi Paul,

R267[7:4] are reserved as it is IP related and also not for modification. They are internally updated by TICS Pro when config is configured.

R222, the register name is REF0_HOLD_CNTSTRT_BY2; the register field is PRIREF_FREQ_DET_10.

I will check the files with 1PPS input to confirm the output reading.

-Riley

Hi, is there any update from your previous response? We have two files - one works and one does not. R260 bit 4 plays a major part in this '0' for  fail and '1' for pass. Above all, this is the area that we would like a response to. Out firmware needs to be committed next week.  Thanks Paul

Hi Paul,

I've tested with both files and can see the outputs lock with correct frequency (10MHz).

Note that with 1PPS input, the lock time is longer compared to 10MHz input. When the input is present, it will be validated, once PRIREF_VALSTAT = 1, the device would start locking and clear LOFL & LOPL. With 1PPS, LOPL is clear at a slower rate than LOFL (a few mins) and during this time, it might experience frequency drifting on the output, but once it locks (LOPL =0, LOFL =0), it would be at correct output frequency.

The current setting has 1PPS phase detector at 2.46us which also accounts for XO ppm error. Perhaps the total ppm error from XO and input are higher than this threshold so the device couldn't clear LOFL, LOPL. You could try supply XO and 1PPS from the same source to minimize this total ppm error so the input can stay within the phase detect threshold to clear LOPL.

-Riley

Hi Riley, Thankyou for the response. We have a fixed 12.8MHz oscillator and the 1pps on SEC/PRI come from external modules. Maybe on this brd our OSC is slightly out in terms of ppm?... The other major point is the R260 register - this appears to solve our issue but we don't know why..

Thankyou Paul