Hello,
I am having trouble with the digital/analog delay feature of the LMK04906. I am using two of these chips, both configured in Dual PLL, Internal VCO, 0-Delay Mode. Both devices receive 10MHz clock input and are configured to produce 160MHz outputs. The clock output from Device 1 is buffered externally and connected to its own feedback input (CLKin1) and also to the feedback input of Device 2. The goal of this is to have a close and fixed relationship between the outputs of both devices that can be made nearly equal with the addition of delay on the output of Device 2.
My understanding of digital delay is that I should see a phase shift in the output of Device 2 (relative to the output of Device 1) when changing the value in the digital delay register for the corresponding clock output and toggling SYNC. The clock outputs have a fixed phase relationship to one another, but the phase of Device 2 always reappears unaffected after changing register delay values and toggling SYNC. Changing the analog delay also does nothing. I've tried the following:
Made sure EN_SYNC is enabled.
Set SYNC_EN_AUTO and written to the clock output register (R4) directly.
Made sure NO_SYNC_CLKoutX is disabled (for the corresponding output).
Triggering SYNC by toggling the polarity of the SYNC_TYPE bit instead of directly with the input of the device.
Tried with "Half Step" both Enabled and Disabled.
Is there something I am misunderstanding about the usage of this feature?
