CDCE72010: Phase Locked Clock Generation

I have a few TI AFE/ADCs on multiple boards. I want the clock driving these ADCs to be programmable so that I can change the sampling rate and I want it to be locked to an external reference so that the ADCs across boards are phase locked. And I need this to be relatively low jitter. Right now in my application I was planning on having a crystal on board and an external clock coming into the board. Both of these feed into a Xilinx FPGA and I use an MCMM core in the FPGA to select the external reference as my reference if its there and the crystal as my reference if its not and then generate my ADC clock with this. The current problem I have though is the jitter on this output clock is too high for my liking. I've looked into some jitter cleaners such as LMK048X, CDCE72010, and CDCM7005. My understanding of these is that they take in a primary and secondary reference clock as well as a tunable VCO. The VCO is what chooses the output frequency and the output clock gets phase locked to the input reference by fine tuning the VCO via feedback. Is this correct or do I have it backwards? If this is correct then this means I can't program the output frequency, it will be set by VCO I pick, which is acceptable if that is the only option, but not ideal. If this is correct then are there any requirements on the jitter of the input reference in order to meet the output jitter specs? If I have this backwards, and the reference choses the frequency then I probably can't use these chips since I won't be able to phase lock VCOs across chips. As an alternative could I use something like the LMX2594? I feed in my reference and program the frequency I want and the output is phase locked to my reference, which achieves my goal. The only thing this is missing is the dual reference. If I did that in the FPGA and fed the selected reference back out (so lots of jitter) is there a jitter requirement on the reference input to this chip to achieve the specified phase noise? If I can use this chip, and it has an input jitter requirement that I do not meet, does TI have a clock buffer type chip that can take in a primary and secondary and spit out the primary if it exists and the secondary if not?

Thanks,

Ryan