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LMK04832: 4-wire SPI - MISO - RESET/GPO serial data out HIGH IMPEDANCE

Christoph Gollinger
Intellectual 275 points
Part Number: LMK04832

Tool/software:

Hello,

we are using the LMK04832 together with other devices on a 4-wire SPI BUS.

As MISO / serial data out of the LMK04832 we use RESET/GPO. This is shared with MISO pins of other devices.

According the datasheet of the LMK04832, by changing the RESET_TYPE in Register 0x14A the behavior of this pin can be changed.

Here it is decribed that the pin can not be set to high impedance.

When using RESET_TYPE= 6 (0x06) Output (open-drain) the output pulls to LOW level. This did not help us.

We were interested to see how the pin behaves when using RESET_TYPE=5(0x05) or 7(0x07)

To our pleasant surprise, with RESET_TYPE=7(0x07) the output appears to be high impedance.

Could you please doublecheck and confirm this?

This would be very helpful.

Thank you and best regards

Christoph

  • 0
    TI__Mastermind 33580 points

    While I know for a fact that 0x07 is actually used for internal purposes and should NOT be treated as a high-impedance option, I'm not sure if 0x05 is connected to anything internally. I'm going to check and get back to you when I find out.

  • +1 in reply to Derek Payne
    TI__Mastermind 33580 points

    I have reviewed the digital logic behavior for the output pin driver and signal decoder. It is my understanding that:

    • RESET_TYPE = 0x05 is connected to the PMOS variant of open-drain mode in the output channel. So there's cases where this mode would short the pin to VCC. I think if you were to set RESET_MUX to 0x00 (Logic Low) and RESET_TYPE to 0x05 (undisclosed PMOS open drain), it would reliably tri-state.
    • RESET_TYPE = 0x07 is connected to internal test signals, and the pin driver is disconnected. Conveniently, it appears that the default settings for the test mode mux holds the output of the mux in high-impedance.

    So it looks like either option would work, even RESET_TYPE=0x07 (provided you aren't modifying the contents of any undisclosed registers).

    I can't actually see inside the PMOS open-drain variant circuit implementation, so I can't tell if the driver implements this function correctly. You may want to verify this behaves as expected with a pulldown resistor and a SPI query to the device. But if it works as expected (i.e. just a pulldown version of the disclosed open-drain), setting RESET_MUX to logic low and RESET_TYPE to PMOS open drain would reliably tri-state the driver.

    The test signal mux defaulting to tri-state seems like a reliable bet in all cases. I don't see any drawbacks. I think both options would work, but this is probably the easier choice.

  • 0 in reply to Derek Payne
    Intellectual 275 points

    Hello Derek,
    thank you very much.
    We did not change other disclosed registers, so it looks like the RESET_TYPE=0x07 seems to be a reasonable easy workaround.

    I do not know if it is difficult to implement a HIGH Impedance of the "MISO" signal on /CS not active, but i think this would help users of the device very much!
    At least in our use-case.


    Best regards
    Christoph

  • 0 in reply to Christoph Gollinger
    TI__Mastermind 33580 points
    Christoph Gollinger said:
    I do not know if it is difficult to implement a HIGH Impedance of the "MISO" signal on /CS not active, but i think this would help users of the device very much!

    I strongly agree, and for the last few years I've taken many opportunities to communicate the need for Hi-Z MISO on CS deassert to our designers whenever we begin specifying new products. It's been tremendously irritating for internal projects as well, having to juggle extra registers to achieve something that should be the default behavior.

    Now that we know how this works in greater detail, I'll also do what I can to get the tri-stating behavior of RESET_TYPE=0x07 (and equivalent behaviors on other GPIO) documented in the datasheet.