LMK01000: use of LMK01000 for JESD204 fanout buffer and SYSREF divider

Part Number: LMK01000

Tool/software:

Hi 

I consider using the LMK01000 for JESD204 fanout buffer and SYSREF divider.

input clock 120MHz

output clocks 120MHz:

------------------------------

2 x LVPECL

2x LVDS

output clocks SYSREF - 8MHz with delay adjustment

---------------------------------------------------------------------

1 x LVPECL

1 X LVDS 

it is stated that "Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay"

is the 150ps is relevant also for 120MHz input?

any relation between the clock input period to the delay adjustment?

please advise

best regards

shay