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Documentation to the CDCE62002

Julius Nyers
Prodigy 70 points
Other Parts Discussed in Thread: CDCE62002, CDCE62005, TLK10002

I was unable to find in the technical documentation to the CDCE62002, what is the phase delay of the produced clock in case of 1:1 reference/output ratio. What is the phase RMS in the case. (Jitter cleaner of 40 MHz in this case with external phase loop). Sincerely - Jiri Kral

  • 0
    TI__Expert 4150 points

    Hi Jiri & Julius,

    The phase delay from device input to device outputis not deterministic for this device. If you can generate a sync signal, you could consider using the CDCE62005, as it has a sync output and allows the output has to be delay minimized to the occurence of that sync singal.

    Concerning jitter, you can expect 2-3ps-rms jitter (12kHz-20MHz integration range] for this device (assumes your loop bandwidth is <1kHz). It will of course depend how you design your loop filter and also a bit on how noisy the reference is. The device works well as a jitter cleaner for the TLK10002, a 10G serdes. 

     

    Best regards, Fritz