CDCEL913: Design Verification of Clock generator

Adarsh Verma

Part Number: CDCEL913
Other Parts Discussed in Thread: SN65DSI83-Q1, , SN65DSI83, CDCE913

Tool/software:

Dear Expert,

We are currently utilizing the SN65DSI83-Q1 as our LVDS converter. However, we have encountered issues with noise and jitter in the clock signal generated from the SOM. To address this, we have decided to implement the CDCEL913 Clock Generator as an external reference clock. Enclosed are the block diagram and schematic for the clock generator.

Could you please advise if a pull-up resistor is necessary for the LVDS_REFCLK? Additionally, are there any other modifications required for our design?

We are also experiencing a PLL unlock message in the SN65DSI83, which is resulting in the output being turned off.

Thank you,
Adarsh Verma

11 days ago

0 Kadeem Samuel 11 days ago

TI__Genius 13720 points

Adarsh,

I would recommend for the CDCE913 either using a separate ferrite bead for VDDOUT or using the same ferrite bead for all VDD & VDDOUT, rather than keeping VDDOUT straight from the supply.
I have re-assigned this to the proper team for the SN65DSI83 questions.

Thanks,
Kadeem

0 Adarsh Verma 10 days ago in reply to Kadeem Samuel

Prodigy 20 points

Thanks Kadeem

0 Adarsh Verma 8 days ago in reply to Kadeem Samuel

Prodigy 20 points

Hi Kadeem,

I am yet to receive any response from the other team.

Regards,
Adarsh Verma

0 Ryan Kitto 7 days ago in reply to Adarsh Verma

TI__Genius 16850 points

Hi Adarsh,

Sorry for the delay in answer, the change in organization caused this thread after the original response caused this thread to fly under our radar. I have assigned a member of your team to this thread and you should get a response from a team member tomorrow, July 5th, due to the US holiday today.

Thanks,

Ryan

0 Vishesh Pithadiya 6 days ago in reply to Ryan Kitto

TI__Genius 13660 points

Hey Aadarsh,

Our implementation of the DSI83 REFCLK can be seen here.

For more info on the design please have a look at pages 8-11 on the EVM users guide.

EVM users guide: https://www.ti.com/lit/ug/sllu221/sllu221.pdf?ts=1720199850362&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN65DSI83

Let me know if you have any more questions.

0 Adarsh Verma 4 days ago in reply to Vishesh Pithadiya

Prodigy 20 points

Hi Vishesh,

Thank you for your response. We have reviewed the information provided but noticed that the issue regarding PLL Unlock was not addressed. Could you please provide clarification or additional details on this matter?

Thank you for your assistance.

Best regards,
Adarsh Verma

0 Vishesh Pithadiya 4 days ago in reply to Adarsh Verma

TI__Genius 13660 points

Hey Adarsh,

When there is a PLL unlock it means that the reference clock signal is not being detected by the internal PLL.

Are you ale to send the register config of the device? This is most likely due to an incorrect register setting in the DSI83. Also are you using the DSI tuner tool to configure the registers.

DSI Tuner Tool Link (Needs java to run): https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1382976/faq-sn65dsi8x-programming-tools?tisearch=e2e-sitesearch&keymatch=sn65dsi85#

You need to make sure the input and output timings are the same. Can you confirm the output of the REFCLK at 27MHz via a scope capture?

0 Adarsh Verma 10 hours ago in reply to Vishesh Pithadiya

Prodigy 20 points

Hi Vishesh,

We have not yet implemented the reference clock in our design. Attached below is the current register configuration file, which uses the clock from the System on Module (SOM).

After using the DSI Tuner, we discovered that three values (0x2C, 0x30, 0x34) are incorrect. After correcting these values, our build is starts failing.

Best regards,
Adarsh Verma

0 Vishesh Pithadiya 1 hour ago in reply to Adarsh Verma

TI__Genius 13660 points

Hey Adarsh,

What is the DSI data rate/ clock speed you are using?

Are you using the correct divider value? Based off of the registers your DSI signal is between 190 and 195MHz and you're diving by 2. This means that your LVDS source is 95 - 97.5Mhz. However your LVDS clock range is set to 62.5 - 87.5.

It also seems that the PLL is disabled 0x0D = 00.

Are you able to get the internal color bar to work?

Can you send the LVDS panel spec?

What is the status of the error register 0xE1 when display isn't working.

Here is an FAQ guiding you through the debug process. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85?tisearch=e2e-sitesearch&keymatch=sn65dsi83#

Let me know if you any questions.

Clock & timing

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CDCEL913: Design Verification of Clock generator