CDCEL913: Design Verification of Clock generator

Adarsh,

I would recommend for the CDCE913 either using a separate ferrite bead for VDDOUT or using the same ferrite bead for all VDD & VDDOUT, rather than keeping VDDOUT straight from the supply.
I have re-assigned this to the proper team for the SN65DSI83 questions.

Thanks,
Kadeem

Thanks Kadeem

Hi Kadeem,

I am yet to receive any response from the other team. 

Regards,
Adarsh Verma

Hi Adarsh,

Sorry for the delay in answer, the change in organization caused this thread after the original response caused this thread to fly under our radar. I have assigned a member of your team to this thread and you should get a response from a team member tomorrow, July 5th, due to the US holiday today.

Thanks,

Ryan

Hi Vishesh,

Thank you for your response. We have reviewed the information provided but noticed that the issue regarding PLL Unlock was not addressed. Could you please provide clarification or additional details on this matter?

Thank you for your assistance.

Best regards,
Adarsh Verma

Hey Adarsh,

When there is a PLL unlock it means that the reference clock signal is not being detected by the internal PLL.

Are you ale to send the register config of the device? This is most likely due to an incorrect register setting in the DSI83. Also are you using the DSI tuner tool to configure the registers. 

DSI Tuner Tool Link (Needs java to run): https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1382976/faq-sn65dsi8x-programming-tools?tisearch=e2e-sitesearch&keymatch=sn65dsi85#

You need to make sure the input and output timings are the same. Can you confirm the output of the REFCLK at 27MHz via a scope capture?

Hi Vishesh,

We have not yet implemented the reference clock in our design. Attached below is the current register configuration file, which uses the clock from the System on Module (SOM).

After using the DSI Tuner, we discovered that three values (0x2C, 0x30, 0x34) are incorrect. After correcting these values, our build is starts failing.

Best regards,
Adarsh Verma

Hey Adarsh,

What is the DSI data rate/ clock speed you are using?

Are you using the correct divider value? Based off of the registers your DSI signal is between 190 and 195MHz and you're diving by 2. This means that your LVDS source is 95 - 97.5Mhz. However your LVDS clock range is set to 62.5 - 87.5.

It also seems that the PLL is disabled 0x0D = 00.

Are you able to get the internal color bar to work?

Can you send the LVDS panel spec?

What is the status of the error register 0xE1 when display isn't working.

Here is an FAQ guiding you through the debug process. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/852871/faq-sn65dsi84-no-display-output-with-sn65dsi83-sn65dsi84-sn65dsi85?tisearch=e2e-sitesearch&keymatch=sn65dsi83#

Let me know if you any questions.

Attached below are the specifications for the LVDS panel. The clock requirement for our LVDS panel is 62.58 MHz. Based on our calculations, the minimum DSI clock frequency needed is 187.74 MHz.

During the initialization process, we enable the PLL, and our internal color bar is operational. However, while the status of register 0xE1 remains 00, register 0xE5 is flagged (refer to the I2C dump below).



(LVDS spec sheet)


(I2C Dump)

Adarsh Verma said:

During the initialization process, we enable the PLL, and our internal color bar is operational.

When using the internal color bar what is the clock source? 

If you are looking to use REF CLK for the data, then the register setting should be this based off of the following calculations

Are my assumptions correct in the tuner?

Hi Vishesh,

When we are using the internal color bar our clock source is derived from the SOM.

Regards 

Adarsh Verma

Vishesh Pithadiya said:

Are my assumptions correct in the tuner?

Were the timings in the script correct?

Adarsh Verma said:

When we are using the internal color bar our clock source is derived from the SOM.

Try to use the ref clock as the source for your DSI clock. Additionally, it seems that the panel you are using has an LVDS clock frequency of 62.58MHz. Try using a oscillator with a compatible frequency. At best with a 20MHz crystal, there will still be a 2MHz delta. 

Are you able to use the DSI83Q1-EVM to verify that the issue has to do with clock jitter?