LMK04828: LMK04828: Default clock frequencies and their power levels

Venkatesh Konduru

Part Number: LMK04828

Tool/software:

Hi,

Please share LMK04828 default clock frequencies at all ports and their power level with out any configuration from FPGA!!

Thanks In Advance

over 1 year ago

0 William Pfennigwerth over 1 year ago

TI__Expert 8421 points

Venkatesh,

Section 9.7.2 of the datasheet give the POR (Power On Reset) values that act as the default configuration at power on. Consult this register map for all clock frequencies, and output types.

Regards,

Will

0 Venkatesh Konduru over 1 year ago in reply to William Pfennigwerth

Prodigy 20 points

sir,

by default LVDS mode is there but we are getting 180mV only ,what could be the issue? Please let me know!!

Thanks In advance

0 William Pfennigwerth over 1 year ago in reply to Venkatesh Konduru

TI__Expert 8421 points

Venkatesh,

I just turned on a LMK04828EVM in our lab, and was seeing the expected LVDS power level, in my case ~ 375 mV single ended and ~ 860 mV differential measurement, which checks out with the datasheet expectation.

I did my measurement by connecting the P and N terminals to the oscilloscope without a termination resistor between. With an oscilloscope that has a 50 ohm termination per connection. How were you measuring the output signal?

Regards,

Will

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LMK04828: LMK04828: Default clock frequencies and their power levels