• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 752 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04821: Synchronizing SYSREF signals from LMK04821 on multiple boards

user4997485
Prodigy 20 points
Part Number: LMK04821
Other Parts Discussed in Thread: LMK04816, LMK04803, LMK04906, LMK04208, LMK04832

Tool/software:

Hello，

I have a question about synchronizing multiple boards, each with one ADC, one LMK04821, and one FPGA.
Here's what I want to do:
・The interface between the AD converter and FPGA is JESD204B.
・The SYSREF mode for LMK04821 is planned to be SYSREF Pulser.
・The reference clock and synchronization signal are distributed to each board in phase using each LMK04821.
・The synchronization signal should be supplied to the SYNC/SYSRE_REQ pin or CLKin0 pin of each LMK04821.
・We would like to use this synchronization signal to simultaneously generate a SYSREF signal from the SDCLKout pin of each LMK04821 to synchronize the AD conversion of each board.

Question 1
Are there any problems with synchronizing using the above method?

Question 2
I cannot find any specification in the data sheet for the input timing of the synchronous signal supplied to the SYNC/SYSRE_REQ pin or CLKin0 pin.
How should I consider the setup time/hold time and the length of the synchronous signal to be supplied?

Question 3
If a synchronization signal is applied to the SYNC/SYSRE_REQ pin or CLKin0 pin of the LMK04821 on each board at the same time, can a SYSREF signal be generated from the SDCLKout pin of the LMK04821 on each board at the same time?
In that case, how should we consider the timing from the synchronization signal to the generation of the SYSREF signal?

Thank you,

Takayuki

  • 0
    TI__Expert 8421 points

    SAI,

    I will get back to you by Wednesday.

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 8421 points

    Hello,

    I apologize for the delay.

    1) Yes, this approach should work.  You can read our app note here that gives a good overview of what you should be trying to achieve. 

    2/3) I am looking into this and will get back to you tomorrow.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 8421 points

    Hello,

    2) In general we say 10ns.

    3) If the two device are using Zero delay mode and have a phase relationship the with same input phase, then you can do SYSREF re-clocking which will ensure that the SYSREF generation occurs at the exact same time.  Without relocking you will also most likely be able to have synchronized SYSREF outputs, but I am not sure the skew on the SYSREF generation logic.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 20 points

    Hello,

    (1) Understood.

    (2) The answer is insufficient.

    　2-1 Is "10ns" the setup time, the hold time, or both?

    　2-2 Which signal is "10ns" relative to? Please tell me the reference signal.

    　2-3 Please tell me the assertion time of the SYNC signal required for a SYNC event.

    (3) There is something unclear about the answer.

    In "Without relocking you will also...", does "relocking" refer to relocking the PLL? Or does it refer to reclocking the SYNC/CLKin0 route?

    (4) I have a new question regarding this matter.

    In the data sheet for the following model, there is an item called "Clock Output Synchronization" that explains the timing of SYNC operation. Both are the same description.

    　Group A LMK04208 LMK04803,5,6,8 LMK04816 LMK04906

    However, the following models have a "Clock Output Synchronization" item, but no explanation of the timing.

    　Group B LMK04821,6,8 LMK04832

    Question: Is it correct to say that the explanation of the timing of the SYNC operation of group A models can also be applied to group B models?

    Regards,Takayuki

  • 0 in reply to user4997485
    TI__Expert 8421 points

    Takayuki,

    Takayuki, I apologize for the long delay, it took me a while to track down some of these answers. 

    2)

    • We do not have any official data on setup and hold times.  Setup and hold times can also vary a lot based on voltage and ambient temperature.  But in general we say 10ns as a conservative general estimate for either setup or hold time.  Another estimate for setup and hold time is that it is is no greater than half of the period of the clock distribution path frequency.  
    • SYNC should be asserted for at least the length of the period of the clock distribution path frequency.

    3) Sorry, this is a typo, I meant to say reclocking. It refers to reclocking the SYNC/SYSREF path.

    4)Group B is the newer series of JESD204B compliant jitter cleaners.  They have added SYSREF functionality that is combined with the SYNC functionality.  Their setup is slightly different and has new features like reclocking, but in practice is very similar.  Read the SYNC/SYSREF sections of Group B datasheets for more information.

    Regards,

    Will