We are looking at he CDC7005 and have a question in the datasheet:
1. Figure 12 on page 23 shows the phase offset tpho from REF_In to Y output and page 15 shows tpho to be –150 min to +150max. Can you clarify theNote 10 at the bottom of the table?
This is valid for the same frequency of the REF_In and Y output clock, but this –150 to +150ps range is still the limit even if you adjust the delay with the spi controller with table 6 right? If you use delay of 0 ps, it is still not really 0ps, but it must still be –150 to +150ps.
2. If we have a 100Mhz REF_IN and have an 800Mhz VCXO and we create a divide by 8 to get a 100Mhz to compare to the REF_IN, what is the tpho between the REF_IN and the 800 Mhz clock?
3. Can you confirm we can use an 800MHz local VCXO and that the divided down to a 100MHz output that can be locked into a fixed phase relationship to the 100 MHz reference clock and that this phase relationship will survive power cycling.
Here is the overview of the implementation
The plan will be to have a centrally located clock module which will feed 100MHz to the board. The board would then create 800MHz, 400MHz, 200MHz, and 100MHz through the device specified. The phase relationship should be maintained throughout.
On the board, the REF_IN will be driven by the 100MHz clock reference, while the VCXO_IN, VCXO_INB differential pair are driven by a voltage controlled oscillator running at 800MHz (these frequencies are within the acceptable range for the CDC7005). The output of the phase comparator CP_OUT feeds back to the VCXO to adjust the local oscillator and to lock it to the reference. Note that the 800MHz signal is divided down by various dividers, then distributed to the different outputs. In our case we will divide by x1, x2, x4, x8 to generate 800MHz, 400MHz, 200MHz, and 100MHz clocks. A mux MUX_SEL selects one of these to feed into the phase comparator – we will choose the 100MHz signal. We set the phase comparator dividers M=N=1, with 0 phase offset. The logic then locks the 100MHz divided down output to the 100MHz reference. The 200MHz, 400Mhz, and 800MHz then also become locked. If all DEB2 boards get the same 100MHz reference clock, then the 100MHz outputs on the clock divider chips will all be locked in a fixed phase relationship that will persist across power-up. Furthermore, the faster clocks will also be locked together. An input NRESET can be pulsed low to reset all divider counters to 0 in order to re-sync and re-lock the phase of all the clocks. Note the 3 STATUS pins that monitor the reference clock status, local oscillator clock status, and lock status. I would assume that the circuitry that controls the SPI bus interface to this chip would also monitor these status bits and report on them via the PCI-Express bus.
One additional we must ask about is our interpretation of their 7005 schematic to make sure that we are correct that it can be used with an 800MHz local oscillator and that the divided down 100MHz output can be locked into a fixed phase relationship to the 100 MHz reference clock and that this phase relationship will survive power cycling.
Thanks, and Best Regards,
-Tim Starr on behalf of MD@BD
