Tool/software:
Hi TIer
With the previous optimization, we changed the frequency of the phaser, which helped to increase the 64M clock alignment, but did not completely solve it.
1, When sync signal to the PLL, which clock be locked? For example, do we use a 0-delay single pll2 clock that is locked to the oscin pin?
2, if not the clock locked to the oscin pin (160M), is it locked to the Clock Distribution Path internal clock (see configuration should be 320M), This clock is internally larger than our oscin clock
What is the requirement for sync signals? For example, if Clock Distribution Path is 640M, then is my sync signal (given by fpga) to be locked to 640M
Thank you very much.
